soc/amd/stoneyridge: use devicetree ops over pci driver

Stoneyridge is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime. In contrast to the other AMD
SoCs in the coreboot tree the PC driver used the PCI ID of the first HT
PCI device function, so add the ops to the device 0x18 function 0
devicetree entry in this patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I500521701479aa271ebd61e22a1494c8bfaf87fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 12 deletions

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 4549abb89450..7e938964beef 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -310,7 +310,7 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
 	return current;
 }
 
-static struct device_operations northbridge_operations = {
+struct device_operations stoneyridge_northbridge_operations = {
 	.read_resources	  = read_resources,
 	.set_resources	  = set_resources,
 	.enable_resources = pci_dev_enable_resources,
@@ -319,17 +319,6 @@ static struct device_operations northbridge_operations = {
 	.write_acpi_tables = agesa_write_acpi_tables,
 };
 
-static const unsigned short pci_device_ids[] = {
-	PCI_DID_AMD_15H_MODEL_606F_NB_HT,
-	PCI_DID_AMD_15H_MODEL_707F_NB_HT,
-	0 };
-
-static const struct pci_driver family15_northbridge __pci_driver = {
-	.ops	= &northbridge_operations,
-	.vendor = PCI_VID_AMD,
-	.devices = pci_device_ids,
-};
-
 /*
  * Enable VGA cycles.  Set memory ranges of the FCH legacy devices (TPM, HPET,
  * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted.  Set remaining