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| author | Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> | 2023-10-17 09:00:05 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-01-03 10:34:44 +0000 |
| commit | 3329e8893eaef8637b3ebdcf3b46e8adcdb5539a (patch) | |
| tree | 637ec55d5e21fdfc749664b7728a7305a7c09125 /src/soc/amd | |
| parent | 27069e61b0406eae0671b60d7bae8350dbd8bdb7 (diff) | |
| download | coreboot-3329e8893eaef8637b3ebdcf3b46e8adcdb5539a.tar.gz coreboot-3329e8893eaef8637b3ebdcf3b46e8adcdb5539a.tar.bz2 coreboot-3329e8893eaef8637b3ebdcf3b46e8adcdb5539a.zip | |
mb/intel/mtlrvp: add 512KB SI_EC FMAP region
This patch introduces the 512KB SI_EC FMAP region for storing the EC
firmware, a necessary addition to support EC chips without internal
flash memory.
As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction
with the Microchip EC1723, and the changes are verified.
Cq-Depend: chrome-internal:6691498
Cq-Depend: chrome-internal:6741356
BUG=b:289783489
TEST=build "emerge-rex coreboot chromeos-bootimage" is successful.
changes are verified.
EC Log:
23-11-06 17:46:49.564 --- UART initialized after reboot ---
23-11-06 17:46:49.564 [Image: RO, mtlrvpp_m1723_v3.5.142816-ec:6596a3,
os:f660f7,cmsis:42cf18,picolibc:6669e4]
23-11-06 17:46:54.609 D: Power state: S5 --> S5S4
23-11-06 17:46:54.620 D: Power state: S5S4 --> S4
23-11-06 17:46:54.620 D: Power state: S4 --> S4S3
23-11-06 17:46:54.642 I: power state 10 = S3S0, in 0x0087
23-11-06 17:46:54.642 ec:~>: Power state: S3S0 --> S0
Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79209
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions