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authorFelix Held <felix-coreboot@felixheld.de>2023-12-11 16:47:54 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-12-12 18:32:56 +0000
commit919801e5dc544194c767b70d8e3db7f09ecc2f37 (patch)
tree813c95c8ca5e303e91607e9867a82b0c88b30aa3 /src/soc/amd
parentc3d909dbb7562cb4c47f07e00961b4256c863895 (diff)
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soc/amd/genoa/chipset.cb: add missing non-transparent PCI bridges
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d5efa948e8bd993ca4b5af80f664db687b8a766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/genoa/chipset.cb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb
index 17ae9fb27040..df40b650fbdd 100644
--- a/src/soc/amd/genoa/chipset.cb
+++ b/src/soc/amd/genoa/chipset.cb
@@ -115,6 +115,8 @@ chip soc/amd/genoa
device pci 07.1 alias gpp_bridge_1_a off
device pci 0.0 on end # Dummy PCIe function
device pci 0.1 off end #SDXI
+ device pci 0.2 alias primary_NTB_1 off end # Primary PCIe Non-TransparentBridge
+ device pci 0.3 alias secondry_NTB_1 off end # Secondary vNTB
end
end
@@ -156,6 +158,8 @@ chip soc/amd/genoa
device pci 07.1 alias gpp_bridge_2_a off
device pci 0.0 on end # Dummy PCIe function
device pci 0.1 off end
+ device pci 0.2 alias primary_NTB_2 off end # Primary PCIe Non-TransparentBridge
+ device pci 0.3 alias secondry_NTB_2 off end # Secondary vNTB
end
end