soc/amd/morgana: Update pci int defs

Update pci int defs per preview of next ppr after rev 1.52, #57396
Update birman and mayan mainboards to remove deleted PIRQs.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 17 insertions, 30 deletions

diff --git a/src/soc/amd/morgana/acpi/pci_int_defs.asl b/src/soc/amd/morgana/acpi/pci_int_defs.asl
index efdce0b5f843..ddd8edda33aa 100644
--- a/src/soc/amd/morgana/acpi/pci_int_defs.asl
+++ b/src/soc/amd/morgana/acpi/pci_int_defs.asl
@@ -22,10 +22,9 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	PIRG, 0x00000008,	/* Index 6: INTG */
 	PIRH, 0x00000008,	/* Index 7: INTH */
 
-	Offset (0x43),
-	PMMC, 0x00000008,	/* Index 0x43: eMMC */
-
-	Offset (0x62),
+	Offset (0x60),
+	PGSC, 0x00000008,	/* Index 0x60: GEventSci */
+	PGSM, 0x00000008,	/* Index 0x61: GEventSmi */
 	PGPI, 0x00000008,	/* Index 0x62: GPIO */
 
 	Offset (0x70),
@@ -35,7 +34,8 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	PI23, 0x00000008,	/* Index 0x73: I2C3 */
 	PUA0, 0x00000008,	/* Index 0x74: UART0 */
 	PUA1, 0x00000008,	/* Index 0x75: UART1 */
-	PI24, 0x00000008,	/* Index 0x76: I2C4 */
+
+	Offset (0x77),
 	PUA4, 0x00000008,	/* Index 0x77: UART4 */
 	PUA2, 0x00000008,	/* Index 0x78: UART2 */
 	PUA3, 0x00000008,	/* Index 0x79: UART3 */
@@ -51,10 +51,9 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	IORG, 0x00000008,	/* Index 0x86: INTG */
 	IORH, 0x00000008,	/* Index 0x87: INTH */
 
-	Offset (0xC3),
-	IMMC, 0x00000008,	/* Index 0xC3: eMMC */
-
-	Offset (0xE2),
+	Offset (0xE0),
+	IGSC, 0x00000008,	/* Index 0xE0: GEventSci */
+	IGSM, 0x00000008,	/* Index 0xE1: GEventSmi */
 	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
 
 	Offset (0xF0),
@@ -64,7 +63,8 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	II23, 0x00000008,	/* Index 0xF3: I2C3 */
 	IUA0, 0x00000008,	/* Index 0xF4: UART0 */
 	IUA1, 0x00000008,	/* Index 0xF5: UART1 */
-	II24, 0x00000008,	/* Index 0xF6: I2C4 */
+
+	Offset (0xF7),
 	IUA4, 0x00000008,	/* Index 0xF7: UART4 */
 	IUA2, 0x00000008,	/* Index 0xF8: UART2 */
 	IUA3, 0x00000008,	/* Index 0xF9: UART3 */
diff --git a/src/soc/amd/morgana/fch.c b/src/soc/amd/morgana/fch.c
index f9f46494380e..08fbe9816e19 100644
--- a/src/soc/amd/morgana/fch.c
+++ b/src/soc/amd/morgana/fch.c
@@ -46,17 +46,13 @@ const static struct irq_idx_name irq_association[] = {
 	{ PIRQ_SMBUS,	"SMBUS" },
 	{ PIRQ_ASF,	"ASF" },
 	{ PIRQ_PMON,	"PerMon" },
-	{ PIRQ_SD,	"SD" },
 	{ PIRQ_SDIO,	"SDIO" },
 	{ PIRQ_CIR,	"CIR" },
 	{ PIRQ_GPIOA,	"GPIOa" },
 	{ PIRQ_GPIOB,	"GPIOb" },
 	{ PIRQ_GPIOC,	"GPIOc" },
-	{ PIRQ_EMMC,	"eMMC" },
-	{ PIRQ_GPP0,	"GPP0" },
-	{ PIRQ_GPP1,	"GPP1" },
-	{ PIRQ_GPP2,	"GPP2" },
-	{ PIRQ_GPP3,	"GPP3" },
+	{ PIRQ_GSCI,	"GEventSci" },
+	{ PIRQ_GSMI,	"GEventSmi" },
 	{ PIRQ_GPIO,	"GPIO" },
 	{ PIRQ_I2C0,	"I2C0" },
 	{ PIRQ_I2C1,	"I2C1" },
@@ -64,7 +60,6 @@ const static struct irq_idx_name irq_association[] = {
 	{ PIRQ_I2C3,	"I2C3" },
 	{ PIRQ_UART0,	"UART0" },
 	{ PIRQ_UART1,	"UART1" },
-	{ PIRQ_I2C4,	"I2C4" },
 	{ PIRQ_UART4,	"UART4" },
 	{ PIRQ_UART2,	"UART2" },
 	{ PIRQ_UART3,	"UART3" },
diff --git a/src/soc/amd/morgana/include/soc/amd_pci_int_defs.h b/src/soc/amd/morgana/include/soc/amd_pci_int_defs.h
index 2835c09e693e..052074ba1a49 100644
--- a/src/soc/amd/morgana/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/morgana/include/soc/amd_pci_int_defs.h
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Morgana */
-
 #ifndef AMD_MORGANA_AMD_PCI_INT_DEFS_H
 #define AMD_MORGANA_AMD_PCI_INT_DEFS_H
 
@@ -32,22 +30,16 @@
 #define PIRQ_ASF	0x12	/* ASF */
 /* 0x13-0x15 reserved */
 #define PIRQ_PMON	0x16	/* Performance Monitor */
-#define PIRQ_SD		0x17	/* SD */
-/* 0x18-0x19 reserved */
+/* 0x17-0x19 reserved */
 #define PIRQ_SDIO	0x1a	/* SDIO */
 /* 0x1b-0x1f reserved */
 #define PIRQ_CIR	0x20	/* CIR, no IRQ connected */
 #define PIRQ_GPIOA	0x21	/* GPIOa from PAD_FANIN0 */
 #define PIRQ_GPIOB	0x22	/* GPIOb from PAD_FANOUT0 */
 #define PIRQ_GPIOC	0x23	/* GPIOc no IRQ connected */
-/* 0x24-0x42 reserved */
-#define PIRQ_EMMC	0x43	/* eMMC */
-/* 0x44-0x4f reserved */
-#define PIRQ_GPP0	0x50	/* GPPInt0 */
-#define PIRQ_GPP1	0x51	/* GPPInt1 */
-#define PIRQ_GPP2	0x52	/* GPPInt2 */
-#define PIRQ_GPP3	0x53	/* GPPInt3 */
-/* 0x54-0x61 reserved */
+/* 0x24-0x5f reserved */
+#define PIRQ_GSCI	0x60	/* GEventSci Interrupt */
+#define PIRQ_GSMI	0x61	/* GEventSmi Interrupt */
 #define PIRQ_GPIO	0x62	/* GPIO Controller Interrupt */
 /* 0x63-0x6f reserved */
 #define PIRQ_I2C0	0x70	/* I2C0 */
@@ -56,7 +48,7 @@
 #define PIRQ_I2C3	0x73	/* I2C3 */
 #define PIRQ_UART0	0x74	/* UART0 */
 #define PIRQ_UART1	0x75	/* UART1 */
-#define PIRQ_I2C4	0x76	/* I2C4 */
+/* 0x76 reserved */
 #define PIRQ_UART4	0x77	/* UART4 */
 #define PIRQ_UART2	0x78	/* UART2 */
 #define PIRQ_UART3	0x79	/* UART3 */