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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-05-07 20:11:53 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-07 19:02:02 +0000 |
| commit | aa49608a2bf474355f0a7cf767e10326259254ed (patch) | |
| tree | cf105fd3ea9503085c6b32042a214a1ad21c1981 /src/soc/intel/alderlake/chipset.cb | |
| parent | 29405483cedca2035d1d0229a2ec893e53a6dcc9 (diff) | |
| download | coreboot-aa49608a2bf474355f0a7cf767e10326259254ed.tar.gz coreboot-aa49608a2bf474355f0a7cf767e10326259254ed.tar.bz2 coreboot-aa49608a2bf474355f0a7cf767e10326259254ed.zip | |
soc/intel/adl: Add SKU specific power limits support
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.
BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
CPU PL1 = 28 Watts
CPU PL2 = 64 Watts
On adlrvp (682):
CPU PL1 = 45 Watts
CPU PL2 = 115 Watts
On brya (282):
CPU PL1 = 15 Watts
CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index c51f92caae77..7085263b66ca 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -1,4 +1,25 @@ chip soc/intel/alderlake + + register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + }" + + register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 64, + }" + + register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 115, + }" + + register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 30, + }" + device domain 0 on device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end |