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| author | Zhuohao Lee <zhuohao@chromium.org> | 2022-01-20 21:30:12 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 20:45:49 +0000 |
| commit | 09f3b6cf21d735b115d25bf081240979dccd0afc (patch) | |
| tree | 5779523a9039598bcb4a6893d7b06bc09f1e72cf /src/soc/intel/alderlake/include/soc/romstage.h | |
| parent | 9f091608b29526246cb02e79e8b4e8b286824509 (diff) | |
| download | coreboot-09f3b6cf21d735b115d25bf081240979dccd0afc.tar.gz coreboot-09f3b6cf21d735b115d25bf081240979dccd0afc.tar.bz2 coreboot-09f3b6cf21d735b115d25bf081240979dccd0afc.zip | |
mb, soc: change mainboard_memory_init_params prototype
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass
Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/include/soc/romstage.h')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/romstage.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h index 3b51b69d5232..6504d320859f 100644 --- a/src/soc/intel/alderlake/include/soc/romstage.h +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -6,7 +6,7 @@ #include <fsp/api.h> #include <stddef.h> -void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg); +void mainboard_memory_init_params(FSPM_UPD *memupd); void systemagent_early_init(void); /* Board type */ |