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| author | Nick Vaccaro <nvaccaro@google.com> | 2020-09-30 13:05:09 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2020-10-05 18:02:37 +0000 |
| commit | 3b24bb6fc8c2a8b672775b70d020a1a8aa87b8e0 (patch) | |
| tree | 609a656b762fa8c4769da6ca78cf10c0f030f6f6 /src/soc/intel/alderlake/include/soc/romstage.h | |
| parent | 0ed02d00cb129f2aa3959116e1730d4d14da2a60 (diff) | |
| download | coreboot-3b24bb6fc8c2a8b672775b70d020a1a8aa87b8e0.tar.gz coreboot-3b24bb6fc8c2a8b672775b70d020a1a8aa87b8e0.tar.bz2 coreboot-3b24bb6fc8c2a8b672775b70d020a1a8aa87b8e0.zip | |
soc: move mainboard_get_dram_part_num prototype to memory_info.h
BUG=b:169774661, b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify they build successfully.
Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/include/soc/romstage.h')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/romstage.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h index 55469a326b2c..c72c8aa4f847 100644 --- a/src/soc/intel/alderlake/include/soc/romstage.h +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -6,8 +6,6 @@ #include <fsp/api.h> #include <stddef.h> -/* Provide a callback to allow mainboard to override the DRAM part number. */ -const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); |