soc/intel/common: Add SOC specific function to get XHCI USB info

It feels appropriate to define SoC specific XHCI USB info in SoC
specific XHCI source file and an API to get that information instead of
defining it in elog source file. This will help in other situations
where the information is required.

BUG=None
BRANCH=None
TEST=Boot to ChromeOS.

Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 4fc16d589162..6fd08221095f 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -44,6 +44,7 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += uart.c
 smm-y += elog.c
+smm-y += xhci.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += cpu.c
@@ -67,6 +68,7 @@ ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += xdci.c
 ramstage-y += sd.c
+ramstage-y += xhci.c
 
 postcar-y += memmap.c
 postcar-y += mmap_boot.c