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| author | Nico Huber <nico.h@gmx.de> | 2019-05-29 23:33:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-06-03 15:23:49 +0000 |
| commit | 9995418166bc4074de2a99aa50e74f8a88196c39 (patch) | |
| tree | af67d06bed637d45d36ec9fc089c4974e536e682 /src/soc/intel/cannonlake/Kconfig | |
| parent | 10ed374d7d6555992a7434370130d813bfa3ad89 (diff) | |
| download | coreboot-9995418166bc4074de2a99aa50e74f8a88196c39.tar.gz coreboot-9995418166bc4074de2a99aa50e74f8a88196c39.tar.bz2 coreboot-9995418166bc4074de2a99aa50e74f8a88196c39.zip | |
soc/intel: Replace UART_BASE() and friends with a Kconfig
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.
As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.
Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index e524275b8fea..76906b254802 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -223,6 +223,11 @@ config SOC_INTEL_I2C_DEV_MAX default 4 if SOC_INTEL_CANNONLAKE_PCH_H default 6 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex |