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| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-05-07 14:05:33 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-05-09 18:05:00 +0000 |
| commit | d5d89c8a55ee3a57fb30a7bca346076269266cab (patch) | |
| tree | 9b1e8f9711a9f3a8d76a319f7478e06b69642678 /src/soc/intel/cannonlake/Kconfig | |
| parent | 643daed6b54970da4d83055649b6abc2a198a840 (diff) | |
| download | coreboot-d5d89c8a55ee3a57fb30a7bca346076269266cab.tar.gz coreboot-d5d89c8a55ee3a57fb30a7bca346076269266cab.tar.bz2 coreboot-d5d89c8a55ee3a57fb30a7bca346076269266cab.zip | |
soc/intel/cannonlake: Fix pcie clock number
Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.
BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c06b91eb48a6..e524275b8fea 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -183,6 +183,11 @@ config MAX_ROOT_PORTS default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config MAX_PCIE_CLOCKS + int + default 16 if SOC_INTEL_CANNONLAKE_PCH_H + default 6 + config SMM_TSEG_SIZE hex default 0x800000 |