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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-12 13:10:19 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-18 15:23:13 +0000 |
| commit | 28dc7dce83131cdd54cad5b338af2f4b89d8969b (patch) | |
| tree | fefc93f097b84a6afd55b6d33e78a98045b6e936 /src/soc/intel/cannonlake/cpu.c | |
| parent | 4323d262473a1ea09eb3f843c4e856eb5851146f (diff) | |
| download | coreboot-28dc7dce83131cdd54cad5b338af2f4b89d8969b.tar.gz coreboot-28dc7dce83131cdd54cad5b338af2f4b89d8969b.tar.bz2 coreboot-28dc7dce83131cdd54cad5b338af2f4b89d8969b.zip | |
soc/intel: Use config_of_path(SA_DEVFN_ROOT)
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I53324603c9ece1334c6e09d51338084166f7a585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/cpu.c')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7dae6153508b..7eb413caa6b8 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -105,8 +105,8 @@ void set_power_limits(u8 power_limit_1_time) unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + + config_t *conf = config_of_path(SA_DEVFN_ROOT); if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = 28; @@ -234,11 +234,10 @@ static void soc_fsp_load(void) static void configure_isst(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; - if (conf && conf->speed_shift_enable) { + if (conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP * is supported or not. coreboot needs to configure MSR 0x1AA @@ -260,12 +259,7 @@ static void configure_isst(void) static void configure_misc(void) { - struct device *dev = SA_DEV_ROOT; - if (!dev) { - printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n"); - return; - } - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); @@ -367,8 +361,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; /* Set TCC activation offset if supported */ |