diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-23 17:54:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 17:42:45 +0000 |
| commit | 4b2464fc90d60f01b0d890e1a0dc6dcdbd119617 (patch) | |
| tree | d6b552cd62528e73c38a3bfbd5088feb5b7e2170 /src/soc/intel/common/block/acpi/acpi/northbridge.asl | |
| parent | 46a3a044adfc8ec15faafd529e27c718754861c3 (diff) | |
| download | coreboot-4b2464fc90d60f01b0d890e1a0dc6dcdbd119617.tar.gz coreboot-4b2464fc90d60f01b0d890e1a0dc6dcdbd119617.tar.bz2 coreboot-4b2464fc90d60f01b0d890e1a0dc6dcdbd119617.zip | |
arch/x86: factor out and commonize HPET_BASE_ADDRESS definition
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/acpi/acpi/northbridge.asl')
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/northbridge.asl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 89495a9e45ea..be14d180bb6c 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <arch/hpet.h> #include <soc/iomap.h> Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID |