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| author | lilacious <yuchenhe126@gmail.com> | 2023-06-21 23:24:14 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-23 15:06:04 +0000 |
| commit | 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 (patch) | |
| tree | 9dc68ba4ab1d8033939e1a872b374fc2ef3ba504 /src/soc/intel/common/block/cpu | |
| parent | bb4bc777b7b6566cd030f2c4eef4b5e2c8425349 (diff) | |
| download | coreboot-40cb3fe94dacfba0b146aae2be9c03c0a0ddb691.tar.gz coreboot-40cb3fe94dacfba0b146aae2be9c03c0a0ddb691.tar.bz2 coreboot-40cb3fe94dacfba0b146aae2be9c03c0a0ddb691.zip | |
commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cpu')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index f2ae72c38ab2..5f6b6de07cda 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -302,7 +302,7 @@ before_carstage: /* Never reached */ .halt_forever: - post_code(POST_DEAD_CODE) + post_code(POSTCODE_DEAD_CODE) hlt jmp .halt_forever diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 0126a122f680..7532c7d70753 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -20,7 +20,7 @@ bootblock_pre_c_entry: .global cache_as_ram cache_as_ram: - post_code(POST_BOOTBLOCK_CAR) + post_code(POSTCODE_BOOTBLOCK_CAR) movl $(CONFIG_FSP_T_LOCATION), %ebx add $0x94, %ebx @@ -99,7 +99,7 @@ CAR_init_done: /* Never reached */ .halt_forever: - post_code(POST_DEAD_CODE) + post_code(POSTCODE_DEAD_CODE) hlt jmp .halt_forever |