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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-03-03 20:15:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-07 20:32:36 +0000 |
| commit | 7f9ceef51be785781ea4c0035c31d718d590a2fb (patch) | |
| tree | dcb10c0b61fbb2a75ac542e8cf58d1f7b660fd34 /src/soc/intel/common/block/smm | |
| parent | 8034813581ad310d567408f050dfa76d5b29144f (diff) | |
| download | coreboot-7f9ceef51be785781ea4c0035c31d718d590a2fb.tar.gz coreboot-7f9ceef51be785781ea4c0035c31d718d590a2fb.tar.bz2 coreboot-7f9ceef51be785781ea4c0035c31d718d590a2fb.zip | |
intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected
Enable TCO SMIs in common code, if selected by Kconfig. This is needed
for the follow-up commits regarding INTRUDER interrupt.
Tested on X11SSM-F.
Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/smm')
| -rw-r--r-- | src/soc/intel/common/block/smm/smm.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index bef923ac1a4e..ecea47364557 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -63,13 +63,16 @@ void smm_southbridge_enable(uint16_t pm1_events) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * - on eSPI events, unless disabled (does nothing on LPC systems) + * - on TCO events (TIMEOUT, case intrusion, ...), if enabled * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE)) smi_params &= ~ESPI_SMI_EN; + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)) + smi_params |= TCO_SMI_EN; + /* Enable SMI generation: */ pmc_enable_smi(smi_params); } |