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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-29 17:04:24 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-27 09:40:17 +0000 |
| commit | 0185d6d7604f0de5ea16c20860b25b8202a29d0a (patch) | |
| tree | 987dac9b12a71e2abbc851e0bfa411e4acf35017 /src/soc/intel/denverton_ns | |
| parent | dd01e0131a8ba901bedec48844502fe85663390a (diff) | |
| download | coreboot-0185d6d7604f0de5ea16c20860b25b8202a29d0a.tar.gz coreboot-0185d6d7604f0de5ea16c20860b25b8202a29d0a.tar.bz2 coreboot-0185d6d7604f0de5ea16c20860b25b8202a29d0a.zip | |
soc/intel/denverton_ns: Drop `pcidev_path_on_root_debug` usage
Currently, this function is only invoked for the SPI device through
common SoC code. Since both Intel Harcuvar and Scaleway Tagada have
enabled the SPI device in the devicetree, there's no need to use the
debug version of `pcidev_path_on_root`.
Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pci_devs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index 5eac5bddbe0f..0cb4c98ced2f 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -10,7 +10,7 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> -#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #else #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) #endif |