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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-01 08:45:47 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-10 21:57:43 +0000 |
| commit | 46c5f8f1d6d8ba4d3ea292a17b6bab025d543c22 (patch) | |
| tree | c6dc8fa0c8bed1ab64768e70a7358c9afc8b1284 /src/soc/intel/elkhartlake/acpi/southbridge.asl | |
| parent | 77b36abcf6436734f74a40218b83fd82181ffb78 (diff) | |
| download | coreboot-46c5f8f1d6d8ba4d3ea292a17b6bab025d543c22.tar.gz coreboot-46c5f8f1d6d8ba4d3ea292a17b6bab025d543c22.tar.bz2 coreboot-46c5f8f1d6d8ba4d3ea292a17b6bab025d543c22.zip | |
soc/intel/elkhartlake: Switch to runtime generation of Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch elkhartlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/elkhartlake/acpi/southbridge.asl | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 059f220c0c2b..2da44bcb79e5 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -38,9 +38,6 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* EMMC/SD card */ #include "scs.asl" |