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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-05-27 22:48:33 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-04 03:47:51 +0000 |
| commit | 9420e2847e6e3559a5e50eb10206f436b4a14a4f (patch) | |
| tree | 80f85e9853ad09fec828c72c8f7c74a48cb3c78c /src/soc/intel/elkhartlake/chip.h | |
| parent | e219862795958009909c36e3a9298dc07935549b (diff) | |
| download | coreboot-9420e2847e6e3559a5e50eb10206f436b4a14a4f.tar.gz coreboot-9420e2847e6e3559a5e50eb10206f436b4a14a4f.tar.bz2 coreboot-9420e2847e6e3559a5e50eb10206f436b4a14a4f.zip | |
soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
Further add initial Silicon UPD settings for:
- PCIe root ports
- USB
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake/chip.h')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 6b36792bde60..ebe14d5a1720 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -80,8 +80,8 @@ struct soc_intel_elkhartlake_config { uint8_t RMT; /* USB related */ - struct usb2_port_config usb2_ports[16]; - struct usb3_port_config usb3_ports[10]; + struct usb2_port_config usb2_ports[10]; + struct usb3_port_config usb3_ports[4]; /* Wake Enable Bitmap for USB2 ports */ uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ @@ -103,16 +103,29 @@ struct soc_intel_elkhartlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; +/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ + uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; + + /* Probe CLKREQ# signal before enabling CLKREQ# based power management. + * Enable - Default (0) / Disable (1) */ + uint8_t PcieRpClkReqDetectDisable[CONFIG_MAX_ROOT_PORTS]; + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ - uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpAdvancedErrorReportingDisable[CONFIG_MAX_ROOT_PORTS]; + + /* PCIe LTR: Enable - Default (0) / Disable (1) */ + uint8_t PcieRpLtrDisable[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; |