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| author | Subrata Banik <subrata.banik@intel.com> | 2019-04-29 12:37:27 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-05-02 06:02:40 +0000 |
| commit | ff9104eae3512e554b4790b40b0bdd3fca2036b3 (patch) | |
| tree | b5f1fd9a80151dab0150bcd2d395a858dd529fe2 /src/soc/intel/icelake/include/soc/pm.h | |
| parent | d32a4930910dbe5dea47777902fcb966a4854114 (diff) | |
| download | coreboot-ff9104eae3512e554b4790b40b0bdd3fca2036b3.tar.gz coreboot-ff9104eae3512e554b4790b40b0bdd3fca2036b3.tar.bz2 coreboot-ff9104eae3512e554b4790b40b0bdd3fca2036b3.zip | |
soc/intel/icelake: Clear PMCON status bits
This patch ports CB:31902 changes from CNL to ICL.
The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.
Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/include/soc/pm.h')
| -rw-r--r-- | src/soc/intel/icelake/include/soc/pm.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 9caf49fa9af1..44888ec74723 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -168,5 +168,8 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif /* !defined(__ACPI__) */ #endif |