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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-12 18:23:27 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-16 17:24:48 +0200 |
| commit | 1d14b3e926c15027f9272f1e80b8913fef8cf25d (patch) | |
| tree | b3d89ad4bb1b0ea5ac05d1d7dc6cbf26ec93e6c3 /src/soc/intel/skylake/include/soc/smbus.h | |
| parent | b000513741d330947bb832a5835378e35bdfb394 (diff) | |
| download | coreboot-1d14b3e926c15027f9272f1e80b8913fef8cf25d.tar.gz coreboot-1d14b3e926c15027f9272f1e80b8913fef8cf25d.tar.bz2 coreboot-1d14b3e926c15027f9272f1e80b8913fef8cf25d.zip | |
soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include/soc/smbus.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smbus.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index fb13c2d8a9c4..c081cdf3e393 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,17 +17,19 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ -#ifndef _BROADWELL_SMBUS_H_ -#define _BROADWELL_SMBUS_H_ +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 #define HST_EN (1 << 0) #define SMB_RCV_SLVA 0x09 +/* SMBUS TCO base address. */ +#define TCOBASE 0x50 /* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 |