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| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-09-07 10:08:35 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-09-12 08:11:17 +0000 |
| commit | a6a5b25ce4235c4e645d3dc20f8222b1a81c54a3 (patch) | |
| tree | 43012c868fbcf120826c93b486a842c6497b3030 /src/soc/intel/tigerlake | |
| parent | e09917641217fea20257ba88fb7ab29912be22ea (diff) | |
| download | coreboot-a6a5b25ce4235c4e645d3dc20f8222b1a81c54a3.tar.gz coreboot-a6a5b25ce4235c4e645d3dc20f8222b1a81c54a3.tar.bz2 coreboot-a6a5b25ce4235c4e645d3dc20f8222b1a81c54a3.zip | |
cpu/intel: Move is_tme_supported() from soc/intel to cpu/intel
It makes the detection of this feature accessible without the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency.
BUG=288978352
TEST=compilation
Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index dd771655f2af..afcbf2f7117c 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -2,6 +2,7 @@ #include <assert.h> #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h> #include <device/device.h> |