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authorRocky Phagura <rphagura@fb.com>2021-04-03 08:49:32 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-06-04 12:38:32 +0000
commitd4db36e672644ac7f528d12c5ce3539725456085 (patch)
tree54887ccb33b3d62df2a684613006da4275c46d16 /src/soc/intel/xeon_sp/Kconfig
parent3bfa1bde60dc3197c27f60ed7b25f9cbdbd3c4bb (diff)
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src/intel/xeon_sp: add hardware error support (HEST)
This patch adds the ACPI hardware error source table (HEST) support. This involves a few different parts: (1) The ACPI HEST table which is filled with the appropriate fields (2) Reserved memory which is used by runtime SW to provide error information. OS will not accept a HEST table with this memory set to 0. The ASL code to enable APEI bit will be submitted in a separate patch. Tested on DeltaLake mainboard with following options enabled SOC_INTEL_XEON_RAS After boot to Linux, the following will show in dmesg: HEST: Table parsing has been initialized Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/xeon_sp/Kconfig')
-rw-r--r--src/soc/intel/xeon_sp/Kconfig6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 09f72a343a77..a2876b5ae32c 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -2,6 +2,7 @@
source "src/soc/intel/xeon_sp/skx/Kconfig"
source "src/soc/intel/xeon_sp/cpx/Kconfig"
+source "src/soc/intel/xeon_sp/ras/Kconfig"
config XEON_SP_COMMON_BASE
bool
@@ -114,4 +115,9 @@ config HEAP_SIZE
hex
default 0x80000
+config SOC_INTEL_XEON_RAS
+ bool
+ select SOC_ACPI_HEST
+ select SOC_RAS_ELOG
+
endif ## SOC_INTEL_XEON_SP