soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs

Support display of CPX-SP specific HOBs (when CONFIG_DISPLAY_HOBS
is selected, and UPD parameters (when CONFIG_DISPLAY_UPD_DATA is selected).

Such display is used for FSP debugging purpose. It adds small
amount of boot time.

Some UPD display log excerpts:
UPD values for SiliconInit:
  0x04: BifurcationPcie0
  0x03: BifurcationPcie1

Some HOB display log excerpts:
=== FSP HOBs ===
0x758df000: hob_list_ptr
0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF
0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41348
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 63 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c
new file mode 100644
index 000000000000..d3222e65f0a5
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/upd_display.c
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <lib.h>
+
+#define DUMP_UPD(old, new, field) \
+	fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field)
+
+/* Display the UPD parameters for MemoryInit */
+void soc_display_fspm_upd_params(
+	const FSPM_UPD *fspm_old_upd,
+	const FSPM_UPD *fspm_new_upd)
+{
+	const FSP_M_CONFIG *new;
+	const FSP_M_CONFIG *old;
+
+	old = &fspm_old_upd->FspmConfig;
+	new = &fspm_new_upd->FspmConfig;
+
+	printk(BIOS_DEBUG, "UPD values for MemoryInit:\n");
+
+	DUMP_UPD(old, new, DebugPrintLevel);
+	DUMP_UPD(old, new, PchAdrEn);
+
+	hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
+}
+
+/* Display the UPD parameters for SiliconInit */
+void soc_display_fsps_upd_params(
+	const FSPS_UPD *fsps_old_upd,
+	const FSPS_UPD *fsps_new_upd)
+{
+	const FSPS_CONFIG *new;
+	const FSPS_CONFIG *old;
+
+	old = &fsps_old_upd->FspsConfig;
+	new = &fsps_new_upd->FspsConfig;
+
+	printk(BIOS_DEBUG, "UPD values for SiliconInit:\n");
+
+	DUMP_UPD(old, new, BifurcationPcie0);
+	DUMP_UPD(old, new, BifurcationPcie1);
+	DUMP_UPD(old, new, ActiveCoreCount);
+	DUMP_UPD(old, new, CpuMicrocodePatchBase);
+	DUMP_UPD(old, new, CpuMicrocodePatchSize);
+	DUMP_UPD(old, new, EnablePcie0);
+	DUMP_UPD(old, new, EnablePcie1);
+	DUMP_UPD(old, new, EnableEmmc);
+	DUMP_UPD(old, new, EnableGbE);
+	DUMP_UPD(old, new, FiaMuxConfigRequestPtr);
+	DUMP_UPD(old, new, PcieRootPort0DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort1DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort2DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort3DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort4DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort5DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort6DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort7DeEmphasis);
+	DUMP_UPD(old, new, EMMCDLLConfigPtr);
+
+	hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
+}