soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specifics

Intel SPR-SP has its specific way to get the bus number of ubox.
Move the current implementations to CPX-SP and SKX-SP folders.

Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 19 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 628613829a18..b501a3e04fbe 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -60,6 +60,17 @@ bool is_iio_stack_res(const STACK_RES *res)
 	return res->BusBase < res->BusLimit;
 }
 
+uint8_t get_stack_busno(const uint8_t stack)
+{
+	if (stack >= MAX_IIO_STACK) {
+		printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
+		return 0;
+	}
+	const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
+	const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
+	return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
+}
+
 uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 {
 	const IIO_UDS *hob = get_iio_uds();
@@ -69,6 +80,14 @@ uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 	return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
 }
 
+uint32_t get_socket_ubox_busno(uint32_t socket)
+{
+	if (socket == 0)
+		return get_stack_busno(PCU_IIO_STACK);
+
+	return get_socket_stack_busno(socket, PCU_IIO_STACK);
+}
+
 void config_reset_cpl3_csrs(void)
 {
 	uint32_t data, plat_info, max_min_turbo_limit_ratio;