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| author | Chun-Jie Chen <chun-jie.chen@mediatek.corp-partner.google.com> | 2021-09-24 18:41:06 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-05 13:03:10 +0000 |
| commit | 76e0b9d710092f1ad73115643b8bb0dd29f46e59 (patch) | |
| tree | 28b898e9e121af872c2880a7ee44ff87c1cf3864 /src/soc/mediatek/mt8186/Makefile.inc | |
| parent | f1226963a120ee8533e168a12093e08229006db8 (diff) | |
| download | coreboot-76e0b9d710092f1ad73115643b8bb0dd29f46e59.tar.gz coreboot-76e0b9d710092f1ad73115643b8bb0dd29f46e59.tar.bz2 coreboot-76e0b9d710092f1ad73115643b8bb0dd29f46e59.zip | |
soc/mediatek/mt8186: Add PLL and clock init support
Add PLL and clock init code, frequency meter and APIs for
raising little CPU/CCI frequency.
TEST=build pass
BUG=b:202871018
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8186/Makefile.inc')
| -rw-r--r-- | src/soc/mediatek/mt8186/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 366c70676c31..cba4ccfe4020 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -4,6 +4,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c |