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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-07-22 14:56:35 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-07-26 05:05:41 +0000 |
| commit | a1509d45451d4f7eb42a2407dd22f82fd19a4312 (patch) | |
| tree | 07d5604d2a65373603636ceefb9d83b92134b931 /src/soc/nvidia | |
| parent | 7aeb1e627c9a670988137f85fa450a1c5165448c (diff) | |
| download | coreboot-a1509d45451d4f7eb42a2407dd22f82fd19a4312.tar.gz coreboot-a1509d45451d4f7eb42a2407dd22f82fd19a4312.tar.bz2 coreboot-a1509d45451d4f7eb42a2407dd22f82fd19a4312.zip | |
soc/nvidia/tegra124: Increase bootblock size
Verstage even fits in 44K so one can comfortably increase the
bootblock size. This is need for the followup patches that turn
console methods into drivers, which increase the bootblock a little,
but still too much for the the bootblock to fit in the alloted size on
this platform.
Change-Id: If1eaf2b495e3032d156433fd0728134a66f4e49b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56521
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra124/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld index f661d2a25c51..68c70c105455 100644 --- a/src/soc/nvidia/tegra124/memlayout.ld +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -21,8 +21,8 @@ SECTIONS VBOOT2_WORK(0x40009800, 12K) TPM_TCPA_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) - BOOTBLOCK(0x40010000, 30K) - VERSTAGE(0x40017800, 72K) + BOOTBLOCK(0x40010000, 32K) + VERSTAGE(0x40018000, 70K) ROMSTAGE(0x40029800, 89K) TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000) |