soc/*: Rename Makefiles from .inc to .mk

The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.

This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/soc/qualcomm/ipq40xx/Makefile.mk b/src/soc/qualcomm/ipq40xx/Makefile.mk
new file mode 100644
index 000000000000..bd61a62a45c3
--- /dev/null
+++ b/src/soc/qualcomm/ipq40xx/Makefile.mk
@@ -0,0 +1,71 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOC_QC_IPQ40XX),y)
+
+bootblock-y += clock.c
+bootblock-y += gpio.c
+bootblock-$(CONFIG_SPI_FLASH) += spi.c
+bootblock-y += timer.c
+bootblock-y += uart.c
+
+verstage-y += clock.c
+verstage-y += gpio.c
+verstage-y += blsp.c
+verstage-y += i2c.c
+verstage-y += qup.c
+verstage-y += spi.c
+verstage-y += timer.c
+verstage-y += uart.c
+
+romstage-y += clock.c
+romstage-y += blobs_init.c
+romstage-y += gpio.c
+romstage-$(CONFIG_SPI_FLASH) += spi.c
+romstage-y += timer.c
+romstage-y += uart.c
+romstage-y += cbmem.c
+romstage-y += i2c.c
+romstage-y += blsp.c
+romstage-y += qup.c
+
+ramstage-y += blobs_init.c
+ramstage-y += clock.c
+ramstage-y += gpio.c
+ramstage-y += lcc.c
+ramstage-y += soc.c
+ramstage-$(CONFIG_SPI_FLASH) += spi.c
+ramstage-y += timer.c
+ramstage-y += uart.c  # Want the UART always ready for the kernels' earlyprintk
+ramstage-y += usb.c
+ramstage-y += tz_wrapper.S
+
+ramstage-y += blsp.c
+ramstage-y += i2c.c
+ramstage-y += qup.c
+ramstage-y += spi.c
+
+ifeq ($(CONFIG_USE_BLOBS),y)
+
+$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_ELF)) \
+			   $(objcbfs)/bootblock.elf
+	@printf "    CRXBL      $(subst $(obj)/,,$(^)) $(subst $(obj)/,,$(@))\n"
+	@$(CONFIG_SBL_UTIL_PATH)/createxbl.py -f $(CONFIG_SBL_ELF) \
+		-s $(objcbfs)/bootblock.elf -o $@ -a 32 -b 32
+
+endif
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/ipq40xx/include
+
+# List of binary blobs coreboot needs in CBFS to be able to boot up this SOC
+mbn-files := $(CONFIG_CDT_MBN) $(CONFIG_DDR_MBN) $(CONFIG_TZ_MBN)
+
+# Location of the binary blobs
+mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq40xx
+
+# Create make variables to aid cbfs-files-handler in processing the blobs (add
+# them all as raw binaries at the root level).
+$(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\
+	  $(eval $(f)-file := $(mbn-root)/$(f))\
+	  $(eval $(f)-type := raw))
+
+endif