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| author | Yakir Yang <ykk@rock-chips.com> | 2015-04-29 10:08:12 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-23 08:20:33 +0200 |
| commit | 68f42be887fa0d98400babf30c1738e580d05f67 (patch) | |
| tree | 76479bb3f7aa34965fccb505e4beb81afe2e4e79 /src/soc/rockchip/rk3288/clock.c | |
| parent | 2f88b83ed14847151d3c6ba85ff804e597a7ad76 (diff) | |
| download | coreboot-68f42be887fa0d98400babf30c1738e580d05f67.tar.gz coreboot-68f42be887fa0d98400babf30c1738e580d05f67.tar.bz2 coreboot-68f42be887fa0d98400babf30c1738e580d05f67.zip | |
rockchip/rk3288: add support for hdmi display
this is an brief hdmi driver which config with simple
display parameter, const encoder input & output color
format and 8bit color depth, and only 48KHz audio support.
what's more to prevent TV have not show an right things
before coreboot switch to kernel space, we have to add
an terrible 2s delay to driver (2s come from test many
times), cause we have to wait TV to respond (we got no
flag to check whether it is ready).
BUG=chrome-os-partner:40337
TEST=Booted Veyron Jerry and display normal
BRANCH=None
Change-Id: Icd33467e95de6219e1b614616f0112afc52097b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e5b699aff75a579116aae63d858c834b2f648e8
Original-Change-Id: Iedc87c011c5b62ce5f16a296dd9c3e0c2eaba59b
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272565
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index a2e8d88ef39e..b823e01431a3 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -571,6 +571,17 @@ void rkclk_configure_edp(void) write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15)); } +void rkclk_configure_hdmi(void) +{ + /* enable pclk hdmi ctrl */ + write32(&cru_ptr->cru_clkgate_con[16], RK_CLRBITS(1 << 9)); + + /* software reset hdmi */ + write32(&cru_ptr->cru_softrst_con[7], RK_SETBITS(1 << 9)); + udelay(1); + write32(&cru_ptr->cru_softrst_con[7], RK_CLRBITS(1 << 9)); +} + void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) { u32 div; |