soc/intel/elkhartlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

6 files changed, 26 insertions, 16 deletions

diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc
index b02cebc8bff9..b5f5f2ad7437 100644
--- a/src/soc/intel/elkhartlake/Makefile.inc
+++ b/src/soc/intel/elkhartlake/Makefile.inc
@@ -22,6 +22,7 @@ bootblock-y += p2sb.c
 romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
+romstage-y += pcie_rp.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
@@ -33,6 +34,7 @@ ramstage-y += fsp_params.c
 ramstage-y += gpio.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += systemagent.c
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index 20e46c04d87c..194591d65a9a 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -14,14 +14,10 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 
-static const struct pcie_rp_group pch_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,    .count = 7, .lcap_port_base = 1 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 204d073365d3..817689006c22 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -212,7 +212,6 @@ struct soc_intel_elkhartlake_config {
 	uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
 
 	/* PCIe Root Ports */
-	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 	uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
 
 	/* PCIe output clocks type to PCIe devices.
diff --git a/src/soc/intel/elkhartlake/include/soc/pcie.h b/src/soc/intel/elkhartlake/include/soc/pcie.h
new file mode 100644
index 000000000000..e7a35413a9e0
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/pcie.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_ELKHARTLAKE_PCIE_H__
+#define __SOC_ELKHARTLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+extern const struct pcie_rp_group pch_rp_groups[];
+
+#endif /* __SOC_ELKHARTLAKE_PCIE_H__ */
diff --git a/src/soc/intel/elkhartlake/pcie_rp.c b/src/soc/intel/elkhartlake/pcie_rp.c
new file mode 100644
index 000000000000..40606e9f5033
--- /dev/null
+++ b/src/soc/intel/elkhartlake/pcie_rp.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+const struct pcie_rp_group pch_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,    .count = 7, .lcap_port_base = 1 },
+	{ 0 }
+};
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index c7c71aaaeeb7..d85f29160cea 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -5,8 +5,10 @@
 #include <device/device.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/pcie_rp.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 
@@ -19,9 +21,6 @@ enum {
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_elkhartlake_config *config)
 {
-	unsigned int i;
-	uint32_t mask = 0;
-
 	/*
 	 * If IGD is enabled, set IGD stolen size to 60MB.
 	 * Otherwise, skip IGD init in FSP.
@@ -33,13 +32,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->SaGv = config->SaGv;
 	m_cfg->RMT = config->RMT;
 
-	/* PCIe root port configuration */
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-
-	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
 
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq);