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| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2022-01-16 23:16:24 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-21 15:17:26 +0000 |
| commit | a6d642fa8da4c723a41ad96b317edd9d8e193460 (patch) | |
| tree | 4a86b3fda696062a7c824a648e8ec47edf48cb9d /src/soc | |
| parent | d2ca5be61a9bcf3e246546aa9eaaf87361a0a4ed (diff) | |
| download | coreboot-a6d642fa8da4c723a41ad96b317edd9d8e193460.tar.gz coreboot-a6d642fa8da4c723a41ad96b317edd9d8e193460.tar.bz2 coreboot-a6d642fa8da4c723a41ad96b317edd9d8e193460.zip | |
soc/intel/alderlake: Enable eMMC based on dev enabled
1. Add eMMC device function in pci_devs.h.
2. Enable eMMC device and configuration based on dev enabled.
3. Add SOC acpi name for eMMC.
Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pci_devs.h | 6 |
4 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 3f5c36597a40..b42322684f66 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -110,6 +110,9 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; case PCH_DEVFN_GBE: return "GLAN"; +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + case PCH_DEVFN_EMMC: return "EMMC"; +#endif } return NULL; diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a5543d6364c0..aad45df3cffb 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -419,6 +419,11 @@ struct soc_intel_alderlake_config { * accordingly */ uint8_t HybridStorageMode; +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + /* eMMC HS400 mode */ + uint8_t emmc_enable_hs400_mode; +#endif + /* * Override CPU flex ratio value: * CPU ratio value controls the maximum processor non-turbo ratio. diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8aa20a8dc676..90e6ab25f5d7 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -183,6 +183,14 @@ static const struct slot_irq_constraints irq_constraints[] = { DIRECT_IRQ(PCH_DEVFN_UART2), }, }, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + { + .slot = PCH_DEV_SLOT_EMMC, + .fns = { + ANY_PIRQ(PCH_DEVFN_EMMC), + }, + }, +#endif { .slot = PCH_DEV_SLOT_PCIE, .fns = { @@ -596,6 +604,12 @@ static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + /* eMMC Configuration */ + s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); + if (s_cfg->ScsEmmcEnabled) + s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; +#endif /* Enable Hybrid storage auto detection */ s_cfg->HybridStorageMode = config->HybridStorageMode; } diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 956a021b681c..b7196df0c300 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -166,6 +166,12 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define PCH_DEV_SLOT_EMMC 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0) +#define PCH_DEV_EMMC _PCH_DEV(EMMC, 0) +#endif + #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) |