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| author | Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> | 2023-01-05 15:46:29 +0800 |
|---|---|---|
| committer | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2023-01-10 09:39:51 +0000 |
| commit | 268a18d58c629fd39bf8e77935f49f94352cb9e3 (patch) | |
| tree | ddc5cf8896e09dcb9efece4901618c6ce6565e47 /src/soc | |
| parent | da3812208ea24f9438b7631374d22fc3ccee14bd (diff) | |
| download | coreboot-268a18d58c629fd39bf8e77935f49f94352cb9e3.tar.gz coreboot-268a18d58c629fd39bf8e77935f49f94352cb9e3.tar.bz2 coreboot-268a18d58c629fd39bf8e77935f49f94352cb9e3.zip | |
soc/mediatek/common: Reset the watchdog timer before triggering reset
When the watchdog timer reaches 0, the timer value won't reset to the
default value unless there is an external reset or a kick. It will
result in the watchdog failing to trigger the reset signal.
We kick the watchdog to reset the timer to the default value. Also,
because WDT hardware needs about 94us to synchronize the registers,
add a 100us delay before triggering the reset signal.
BUG=b:264003005, b:264017048
BRANCH=corsola
TEST= Reboot successfully with the following cmd
stop daisydog
sleep 60 > /dev/watchdog&
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com>
Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/wdt_common.h | 5 | ||||
| -rw-r--r-- | src/soc/mediatek/common/wdt.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/wdt_common.h b/src/soc/mediatek/common/include/soc/wdt_common.h index 5587d504e849..6d6d2ba75809 100644 --- a/src/soc/mediatek/common/include/soc/wdt_common.h +++ b/src/soc/mediatek/common/include/soc/wdt_common.h @@ -32,6 +32,11 @@ enum { MTK_WDT_MODE_ENABLE = 1 << 0 }; +/* WDT_RESTART */ +enum { + MTK_WDT_RESTART_KEY = 0x1971 +}; + /* WDT_RESET */ enum { MTK_WDT_SWRST_KEY = 0x1209, diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 7ae4661011ce..663fc2fd3056 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cache.h> +#include <delay.h> #include <device/mmio.h> #include <console/console.h> #include <halt.h> @@ -23,7 +24,9 @@ static inline void mtk_wdt_swreset(void) printk(BIOS_INFO, "%s() called!\n", __func__); dcache_clean_all(); + write32(&mtk_wdt->wdt_restart, MTK_WDT_RESTART_KEY); setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + udelay(100); write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); halt(); |