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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2024-02-14 13:23:28 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-06-08 08:18:26 +0000 |
| commit | ca5254acc0d55199254a270496c955249ad244d1 (patch) | |
| tree | 342666bf51e850062f672a253dcb5a398e4d8979 /src/soc | |
| parent | f0fb3af828b3b457c4487a174440e6f6b6d073ca (diff) | |
| download | coreboot-ca5254acc0d55199254a270496c955249ad244d1.tar.gz coreboot-ca5254acc0d55199254a270496c955249ad244d1.tar.bz2 coreboot-ca5254acc0d55199254a270496c955249ad244d1.zip | |
soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the
equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set.
Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD
as well for Alder Lake.
Setting this FSP-M UPD will cause FSP to properly program sideband
use BSSB_LSx pins for the enabled Type-C ports. Required for proper
DCI debug and TCSS initialization flow.
Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 84f83e3bbe5b..d917e6cdfecc 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -271,6 +271,11 @@ static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); + m_cfg->UsbTcPortEnPreMem = 0; + for (int i = 0; i < MAX_TYPE_C_PORTS; i++) + if (config->tcss_ports[i].enable) + m_cfg->UsbTcPortEnPreMem |= BIT(i); + #if (CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)) || \ (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO)) m_cfg->DisableDynamicTccoldHandshake = |