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| author | Maximilian Brune <maximilian.brune@9elements.com> | 2024-04-15 12:58:29 +0200 |
|---|---|---|
| committer | Maximilian Brune <maximilian.brune@9elements.com> | 2024-06-12 19:16:26 +0000 |
| commit | e437cb5f87a022c5e219ce1aadfd16a2078e0e86 (patch) | |
| tree | f897ad9d9279abc85dbc93ae4d98e7221d71bf60 /src/soc | |
| parent | 61dee38ee05cc039e4f5cf6358140a19571d4a4d (diff) | |
| download | coreboot-e437cb5f87a022c5e219ce1aadfd16a2078e0e86.tar.gz coreboot-e437cb5f87a022c5e219ce1aadfd16a2078e0e86.tar.bz2 coreboot-e437cb5f87a022c5e219ce1aadfd16a2078e0e86.zip | |
soc/sifive/fu540/chip.c: Add RAM resources
Add RAM region so that the payload can be placed in there without
coreboot complaining that the payload doesn't target a RAM region.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id07eae3560ce69cd8a6a695702fa0b4463c50855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81909
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/sifive/fu540/chip.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/sifive/fu540/chip.c b/src/soc/sifive/fu540/chip.c index e33b4a3b0f4a..1733b20aa7a0 100644 --- a/src/soc/sifive/fu540/chip.c +++ b/src/soc/sifive/fu540/chip.c @@ -1,6 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cbmem.h> #include <device/device.h> +#include <soc/addressmap.h> + +static void fu540_read_resources(struct device *dev) +{ + int index = 0; + ram_from_to(dev, index++, FU540_DRAM, (uintptr_t)cbmem_top()); +} + +struct device_operations fu540_cpu_ops = { + .read_resources = fu540_read_resources, +}; struct chip_operations soc_sifive_fu540_ops = { .name = "SIFIVE FU540", |