factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()

Instead of writing to config registers in k8x8xx's dram_enable()
and reading those back in vt8237r_cfg(), factor out generation of
the values and reuse that in both places.

Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

3 files changed, 43 insertions, 49 deletions

diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index 42676b177048..73635105f94e 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -31,31 +31,8 @@
 
 static void vt8237r_cfg(struct device *dev, struct device *devsb)
 {
-	u8 regm, regm3;
-
-	device_t devfun3;
-
-	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
-
-	if (!devfun3)
-		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
-
-	if (!devfun3)
-		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
-
-	if (!devfun3)
-		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
-
-	if (!devfun3)
-		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
-
-	if(!devfun3)
-		die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n");
+	u8 regm3;
+	struct k8x8xx_vt8237_mirrored_regs mregs;
 
 	pci_write_config8(dev, 0x70, 0xc2);
 
@@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
 	pci_write_config8(dev, 0x7c, 0x7f);
 	pci_write_config8(dev, 0x7f, 0x02);
 
-	/* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
-
-	regm = pci_read_config8(devfun3, 0x88);	/* Shadow mem CTRL */
-	pci_write_config8(dev, 0x57, regm);
-
-	regm = pci_read_config8(devfun3, 0x80);	/* Shadow page C */
-	pci_write_config8(dev, 0x61, regm);
-
-	regm = pci_read_config8(devfun3, 0x81);	/* Shadow page D */
-	pci_write_config8(dev, 0x62, regm);
+	k8x8xx_vt8237_mirrored_regs_fill(&mregs);
 
-	regm = pci_read_config8(devfun3, 0x86);	/* SMM and APIC decoding */
-	pci_write_config8(dev, 0xe6, regm);
+	pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl);		/* Shadow mem CTRL */
+	pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c);	/* Shadow page C */
+	pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d);	/* Shadow page D */
+	pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding);		/* SMM and APIC decoding */
 
-	regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
+	regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding;	/* Shadow page E */
 
 	/*
 	 * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
@@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
 		regm3 = 0x0;
 
 	/* Shadow page F + memhole copy */
-	regm = pci_read_config8(devfun3, 0x83);
-	pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
+	pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F));
 
 }
 
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index 9b43a5e57f23..294e3871dd0d 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -30,14 +30,15 @@
 
 static void dram_enable(struct device *dev)
 {
-	msr_t msr;
 	u16 reg;
+	struct k8x8xx_vt8237_mirrored_regs mregs;
 
+	k8x8xx_vt8237_mirrored_regs_fill(&mregs);
 	/*
 	 * Enable Lowest Interrupt arbitration for APIC, enable NB APIC
 	 * decoding, MSI support, no SMRAM, compatible SMM.
 	 */
-	pci_write_config8(dev, 0x86, 0x19);
+	pci_write_config8(dev, 0x86, mregs.smm_apic_decoding);
 
 	/*
 	 * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if
@@ -48,23 +49,22 @@ static void dram_enable(struct device *dev)
 	/* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for
 	 * C0000-C3FFF etc.
 	 */
-	pci_write_config8(dev, 0x80, 0xff);
+	pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c);
 	/* For page D0000-DFFFF */
-	pci_write_config8(dev, 0x81, 0xff);
+	pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d);
 	/* For page E0000-EFFFF */
-	pci_write_config8(dev, 0x82, 0xff);
-	pci_write_config8(dev, 0x83, 0x30);
+	pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding);
+	pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole);
 
-	msr = rdmsr(TOP_MEM);
 	reg = pci_read_config16(dev, 0x84);
 	reg &= 0xf;
-	pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg);
+	pci_write_config16(dev, 0x84, mregs.low_top_address | reg);
 
 	reg = pci_read_config16(dev, 0x88);
 	reg &= 0xf800;
 
 	/* The Address Next to the Last Valid DRAM Address */
-	pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
+	pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl);
 
 	print_debug(" VIA_X_3 device dump:\n");
 	dump_south(dev);
diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h
index a0fb57ab3c16..425aaeb5e85c 100644
--- a/src/southbridge/via/k8t890/k8x8xx.h
+++ b/src/southbridge/via/k8t890/k8x8xx.h
@@ -21,6 +21,31 @@
 #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
 #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
 
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
 #include "k8t890.h"
 
+struct k8x8xx_vt8237_mirrored_regs {
+	u16 low_top_address;
+	u8 rom_shadow_ctrl_pg_c,
+		rom_shadow_ctrl_pg_d,
+		rom_shadow_ctrl_pg_e_memhole_smi_decoding,
+		rom_shadow_ctrl_pg_f_memhole,
+		smm_apic_decoding,
+		shadow_mem_ctrl;
+};
+
+static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){
+	msr_t msr;
+
+	regs->rom_shadow_ctrl_pg_c = 0xff;
+	regs->rom_shadow_ctrl_pg_d = 0xff;
+	regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff;
+	regs->rom_shadow_ctrl_pg_f_memhole = 0x30;
+	regs->smm_apic_decoding = 0x19;
+	msr = rdmsr(TOP_MEM);
+	regs->shadow_mem_ctrl = msr.lo >> 24;
+	regs->low_top_address = msr.lo >> 16;
+}
+
 #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */