diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-02 00:21:01 +0200 |
---|---|---|
committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 10:13:21 +0000 |
commit | d0310faa3bc4d3b62d17d632fbaee98c146eebe0 (patch) | |
tree | 8d3a55eb4135484ae7729f8092876ba36c165a2e /src/southbridge | |
parent | f266dc61743cfce56ea026e66bc88cad8e5de2bb (diff) | |
download | coreboot-d0310faa3bc4d3b62d17d632fbaee98c146eebe0.tar.gz coreboot-d0310faa3bc4d3b62d17d632fbaee98c146eebe0.tar.bz2 coreboot-d0310faa3bc4d3b62d17d632fbaee98c146eebe0.zip |
sb/intel/ibexpeak: Implement PCH function disable in chip_ops
This does the following:
- implement a PCH disable function that will be called by the PCI
drivers as part of their chip_ops
- removes the iobp_x calls as those don't exist on ibexpeak
- complete the devicetree with to be disabled PCI devices for the
chip_ops to be called
- Clean up some code copied from bd82x6x
Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/intel/ibexpeak/Makefile.inc | 4 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 13 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/pch.c | 107 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 3 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/sata.c | 12 |
5 files changed, 110 insertions, 29 deletions
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 97565d6becbf..9caf29fd87bc 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -15,7 +15,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) -ramstage-y += ../bd82x6x/pch.c +ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c ramstage-y += ../bd82x6x/pci.c @@ -35,7 +35,7 @@ ramstage-y += ../bd82x6x/me_status.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += madt.c -smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c +smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 3e1f4a4350d5..ec9b045f2447 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -409,11 +409,6 @@ static void enable_clock_gating(struct device *dev) reg16 |= (1 << 2) | (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); - reg32 = RCBA32(CG); reg32 |= (1 << 31); reg32 |= (1 << 29) | (1 << 28); @@ -500,13 +495,7 @@ static void lpc_init(struct device *dev) pch_power_options(dev); /* Initialize power management */ - switch (pch_silicon_type()) { - case PCH_TYPE_MOBILE5: - mobile5_pm_init (dev); - break; - default: - printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); - } + mobile5_pm_init(dev); /* Set the state of the GPIO lines. */ //gpio_init(dev); diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c new file mode 100644 index 000000000000..9148b44a8e4e --- /dev/null +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci_ops.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include "pch.h" + +/* Set bit in function disable register to hide this device */ +static void pch_disable_devfn(struct device *dev) +{ + switch (dev->path.pci.devfn) { + case PCI_DEVFN(22, 0): /* MEI #1 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); + break; + case PCI_DEVFN(22, 1): /* MEI #2 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI2); + break; + case PCI_DEVFN(22, 2): /* IDE-R */ + RCBA32_OR(FD2, PCH_DISABLE_IDER); + break; + case PCI_DEVFN(22, 3): /* KT */ + RCBA32_OR(FD2, PCH_DISABLE_KT); + break; + case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ + RCBA32_OR(BUC, PCH_DISABLE_GBE); + break; + case PCI_DEVFN(26, 0): /* EHCI #2 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI2); + break; + case PCI_DEVFN(27, 0): /* HD Audio Controller */ + RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); + break; + case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ + case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ + case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ + case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ + case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ + case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ + case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ + case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ + RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); + break; + case PCI_DEVFN(29, 0): /* EHCI #1 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI1); + break; + case PCI_DEVFN(31, 0): /* LPC */ + RCBA32_OR(FD, PCH_DISABLE_LPC); + break; + case PCI_DEVFN(31, 2): /* SATA #1 */ + RCBA32_OR(FD, PCH_DISABLE_SATA1); + break; + case PCI_DEVFN(31, 3): /* SMBUS */ + RCBA32_OR(FD, PCH_DISABLE_SMBUS); + break; + case PCI_DEVFN(31, 5): /* SATA #22 */ + RCBA32_OR(FD, PCH_DISABLE_SATA2); + break; + case PCI_DEVFN(31, 6): /* Thermal Subsystem */ + RCBA32_OR(FD, PCH_DISABLE_THERMAL); + break; + } +} + +void pch_enable(struct device *dev) +{ + u32 reg32; + + if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Disable this device if possible */ + pch_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + +struct chip_operations southbridge_intel_ibexpeak_ops = { + CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge") + .enable_dev = pch_enable, +}; diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index f0e469a3ace7..34f80330bcdd 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -51,9 +51,6 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_smbus(void); void enable_usb_bar(void); diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index c99e944513e5..2d9412ad64de 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -176,15 +176,6 @@ static void sata_init(struct device *dev) sata_port_map ^ 0x3f) << 24) | 0x183); } - /* Set Gen3 Transmitter settings if needed */ - if (config->sata_port0_gen3_tx) - pch_iobp_update(SATA_IOBP_SP0G3IR, 0, - config->sata_port0_gen3_tx); - - if (config->sata_port1_gen3_tx) - pch_iobp_update(SATA_IOBP_SP1G3IR, 0, - config->sata_port1_gen3_tx); - /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00000000); sir_write(dev, 0x28, 0x0a000033); @@ -208,9 +199,6 @@ static void sata_init(struct device *dev) sir_write(dev, 0xc4, 0x0c0c0c0c); sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000); - - pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); - pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } static void sata_enable(struct device *dev) |