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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-08-24 15:12:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-31 10:36:39 +0000 |
| commit | 7fcd4d58ec7ea2da31c258ba9d8601f086d7f8d8 (patch) | |
| tree | 1bddf10cecf4577fee207e0dbc6f7a5c1b10af13 /src/southbridge | |
| parent | 3138faa7cf1b91e0b56ad0b1be6260cf4251a284 (diff) | |
| download | coreboot-7fcd4d58ec7ea2da31c258ba9d8601f086d7f8d8.tar.gz coreboot-7fcd4d58ec7ea2da31c258ba9d8601f086d7f8d8.tar.bz2 coreboot-7fcd4d58ec7ea2da31c258ba9d8601f086d7f8d8.zip | |
device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 266d75c58945..66ec82414fe8 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -171,8 +171,8 @@ static void hudson_lpc_enable_childrens_resources(struct device *dev) reg_var[0] = pci_read_config16(dev, 0x64); struct device *child; - if (dev->link_list) { - for (child = dev->link_list->children; child; child = child->sibling) { + if (dev->downstream) { + for (child = dev->downstream->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; for (res = child->resource_list; res; res = res->next) { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 13f16f874bd9..a1dd16e8cd1e 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -145,8 +145,8 @@ static void pch_pcie_pm_early(struct device *dev) * must be a static device from devicetree.cb. * If one is found assume it's an integrated device and not a PCIe slot. */ - if (dev->link_list) - child = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); + if (dev->downstream) + child = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0)); /* Set slot power limit as configured above */ reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP); |