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| author | Elyes Haouas <ehaouas@noos.fr> | 2023-09-09 10:18:03 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-01-15 19:30:15 +0000 |
| commit | a7f55af995040045875515857d095c021984f7f2 (patch) | |
| tree | edfeec52bbb0c70c8d0de87928245ee9af7f5c82 /src/southbridge | |
| parent | 550f55e4f63dcb6d16132d2f5596e653fe2d1579 (diff) | |
| download | coreboot-a7f55af995040045875515857d095c021984f7f2.tar.gz coreboot-a7f55af995040045875515857d095c021984f7f2.tar.bz2 coreboot-a7f55af995040045875515857d095c021984f7f2.zip | |
sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate
Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77738
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801ix/chip.h | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/chip.h | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 4 |
4 files changed, 13 insertions, 13 deletions
diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index d52a0c2006f5..33f971336855 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -56,12 +56,12 @@ struct southbridge_intel_i82801ix_config { /* IDE configuration */ uint8_t sata_port_map : 6; - unsigned int sata_clock_request : 1; - unsigned int sata_traffic_monitor : 1; + bool sata_clock_request; + bool sata_traffic_monitor; - unsigned int c4onc3_enable:1; - unsigned int c5_enable : 1; - unsigned int c6_enable : 1; + bool c4onc3_enable; + bool c5_enable; + bool c6_enable; unsigned int throttle_duty : 3; diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index d897130e4222..91b7456d54c2 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -142,14 +142,14 @@ bool southbridge_support_c5(void) { struct device *lpc_dev = __pci_0_1f_0; struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; - return config->c5_enable == 1; + return config->c5_enable; } bool southbridge_support_c6(void) { struct device *lpc_dev = __pci_0_1f_0; struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info; - return config->c6_enable == 1; + return config->c6_enable; } static void i82801ix_power_options(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index f12a67e877c6..48ad2124d03b 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -43,11 +43,11 @@ struct southbridge_intel_i82801jx_config { /* IDE configuration */ uint8_t sata_port_map : 6; - unsigned int sata_clock_request : 1; + bool sata_clock_request; - unsigned int c4onc3_enable:1; - unsigned int c5_enable : 1; - unsigned int c6_enable : 1; + bool c4onc3_enable; + bool c5_enable; + bool c6_enable; unsigned int throttle_duty : 3; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e93502fa0d76..7cff33a26131 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -144,14 +144,14 @@ bool southbridge_support_c5(void) { struct device *lpc_dev = __pci_0_1f_0; struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info; - return config->c5_enable == 1; + return config->c5_enable; } bool southbridge_support_c6(void) { struct device *lpc_dev = __pci_0_1f_0; struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info; - return config->c6_enable == 1; + return config->c6_enable; } static void i82801jx_power_options(struct device *dev) |