diff options
| author | Ivy Jian <ivy_jian@compal.corp-partner.google.com> | 2021-04-23 11:26:47 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:29:15 +0000 |
| commit | c20f33960cbf57aa33a1b8ea32799511dabbb18c (patch) | |
| tree | a1ef0231afb5ea0906cba4e4ec35e0d83fd4119d /src/vendorcode/amd | |
| parent | 4f4eba9149d1f087cdfdff4194b8762263114117 (diff) | |
| download | coreboot-c20f33960cbf57aa33a1b8ea32799511dabbb18c.tar.gz coreboot-c20f33960cbf57aa33a1b8ea32799511dabbb18c.tar.bz2 coreboot-c20f33960cbf57aa33a1b8ea32799511dabbb18c.zip | |
mb/google/mancomb: PCIe GPIOs - enable enables, disable resets
To train PCIe devices, the devices need to be enabled and taken out of
reset. This patch does the bare minimum needed to train PCIe. It is
not intended to handle timings, which will be addressed later.
Copy the enables for WLAN into early GPIO Init so that they're
enabled before FSP-M runs and trains the PCIe busses.
Again, this patch is the minimum to let the FSP train the PCIe busses.
BUG=b:182202136
TEST=Boot guybrush from NVME.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/vendorcode/amd')
0 files changed, 0 insertions, 0 deletions