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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-04-06 18:28:07 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-04-27 10:56:47 +0000 |
| commit | 5cf02a4ecdcf4c93a281289fa51dff90bdddd36f (patch) | |
| tree | 2e540fee843c1c636585b064288528be8606f6a0 /src/vendorcode | |
| parent | fd016126e46509e71b8890e21bf0a29e1d1523b0 (diff) | |
| download | coreboot-5cf02a4ecdcf4c93a281289fa51dff90bdddd36f.tar.gz coreboot-5cf02a4ecdcf4c93a281289fa51dff90bdddd36f.tar.bz2 coreboot-5cf02a4ecdcf4c93a281289fa51dff90bdddd36f.zip | |
lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks
hardwaremain.c is the common ramstage entry to all platforms so move
out ACPI code generation (x86 specific) to boot state hooks.
Another reason to do this is the following:
On some platforms that start in dram it makes little sense to have
separate stages. To reduce the complexity we want to call the ramstage
main function instead of loading a full stage. To make this scheme
more maintainable it makes sense to move out as much functionality
from the 'main' function as possible.
Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63414
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/google/chromeos/chromeos.h | 1 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/gnvs.c | 6 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index cd3b6035070a..5db78671ce93 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -26,7 +26,6 @@ void mainboard_prepare_cr50_reset(void); void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); -void chromeos_init_chromeos_acpi(void); /** * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index faaa646b4357..3d66aa3f79d3 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -2,7 +2,7 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <bootmode.h> +#include <bootstate.h> #include <types.h> #include <string.h> #include <stdlib.h> @@ -32,7 +32,7 @@ static size_t chromeos_vpd_region(const char *region, uintptr_t *base) return region_device_sz(&vpd); } -void chromeos_init_chromeos_acpi(void) +static void chromeos_init_chromeos_acpi(void *unused) { size_t vpd_size; uintptr_t vpd_base = 0; @@ -58,6 +58,8 @@ void chromeos_init_chromeos_acpi(void) } } +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, chromeos_init_chromeos_acpi, NULL); + void chromeos_set_me_hash(u32 *hash, int len) { if ((len*sizeof(u32)) > sizeof(chromeos_acpi->mehh)) |