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authorMartin Roth <martinroth@chromium.org>2021-08-31 17:46:27 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-09-16 22:46:52 +0000
commit76643f0dfb65d9ceca3189cf71d6593001fa692f (patch)
treeaacc8a2bb5b8c80a4289b1dc70b11913d7908a46 /src
parent9ed8e383660062e08b5da8d322d39f613ffef375 (diff)
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mb/google/guybrush: If not using PCIe WWAN, disable the port
Check to see if the PCIe slot needs to be activated for the WWAN card. If it doesn't, leave it unused so it will be powered off and not do the PCIe training. BUG=b:193036827 TEST=Boot & Reboot guybrush with both PCIe & USB WWAN cards. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/guybrush/port_descriptors.c98
1 files changed, 93 insertions, 5 deletions
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index e1c78da449d3..b745fc1317de 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -7,7 +7,7 @@
#include <types.h>
/* All PCIe Resets are handled in coreboot */
-static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
+static const fsp_dxio_descriptor guybrush_czn_pci_wwan_descriptors[] = {
{ /* WLAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
@@ -64,7 +64,89 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.clk_req = CLK_REQ3,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
- { /* TODO: remove this temporay workaround */
+ { /* TODO: remove this temporary workaround */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 8,
+ .end_logical_lane = 11,
+ .device_number = PCIE_GPP_BRIDGE_2_DEV,
+ .function_number = PCIE_GPP_2_4_FUNC,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ5,
+ .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ },
+ { /* TODO: remove this temporary workaround */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 16,
+ .end_logical_lane = 23,
+ .device_number = PCIE_GPP_BRIDGE_1_DEV,
+ .function_number = PCIE_GPP_1_0_FUNC,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ6,
+ .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ }
+};
+
+/* All PCIe Resets are handled in coreboot */
+static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
+ { /* WLAN */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 0,
+ .end_logical_lane = 0,
+ .device_number = PCI_SLOT(WLAN_DEVFN),
+ .function_number = PCI_FUNC(WLAN_DEVFN),
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ0,
+ .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ },
+ { /* SD */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 1,
+ .end_logical_lane = 1,
+ .device_number = PCI_SLOT(SD_DEVFN),
+ .function_number = PCI_FUNC(SD_DEVFN),
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ1,
+ .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ },
+ { /* WWAN */
+ .engine_type = UNUSED_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 2,
+ .end_logical_lane = 2,
+ .device_number = PCI_SLOT(WWAN_DEVFN),
+ .function_number = PCI_FUNC(WWAN_DEVFN),
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ2,
+ .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ },
+ { /* NVME */
+ .engine_type = PCIE_ENGINE,
+ .port_present = true,
+ .start_logical_lane = 4,
+ .end_logical_lane = 7,
+ .device_number = PCI_SLOT(NVME_DEVFN),
+ .function_number = PCI_FUNC(NVME_DEVFN),
+ .link_aspm = ASPM_L1,
+ .link_aspm_L1_1 = true,
+ .link_aspm_L1_2 = true,
+ .turn_off_unused_lanes = true,
+ .clk_req = CLK_REQ3,
+ .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ },
+ { /* TODO: remove this temporary workaround */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 8,
@@ -75,7 +157,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.clk_req = CLK_REQ5,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
- { /* TODO: remove this temporay workaround */
+ { /* TODO: remove this temporary workaround */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
@@ -121,8 +203,14 @@ void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
- *dxio_descs = guybrush_czn_dxio_descriptors;
- *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors);
+ if (variant_has_pcie_wwan()) {
+ *dxio_descs = guybrush_czn_pci_wwan_descriptors;
+ *dxio_num = ARRAY_SIZE(guybrush_czn_pci_wwan_descriptors);
+ } else {
+ *dxio_descs = guybrush_czn_dxio_descriptors;
+ *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors);
+ }
+
*ddi_descs = guybrush_czn_ddi_descriptors;
*ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors);
}