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| author | Felix Singer <felixsinger@posteo.net> | 2023-11-12 17:35:05 +0000 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-11-13 20:41:37 +0000 |
| commit | c3ec144c103f92190af8816bae084c8002aa89ab (patch) | |
| tree | 503d57d3cf2c5a8f8527779594430eec4e18beb7 /src | |
| parent | affd4567536aabc08f34a3a093f1a95990dfc2e3 (diff) | |
| download | coreboot-c3ec144c103f92190af8816bae084c8002aa89ab.tar.gz coreboot-c3ec144c103f92190af8816bae084c8002aa89ab.tar.bz2 coreboot-c3ec144c103f92190af8816bae084c8002aa89ab.zip | |
mb/libretrend/lt1000: Make use of the chipset devicetree
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I6ba850c783999d06c73137ed77d32fc108a20347
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 53 |
1 files changed, 19 insertions, 34 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 09da24cc2a43..cdddf3d2e6b0 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -161,39 +161,27 @@ chip soc/intel/skylake device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem - device pci 14.0 on end # USB xHCI - device pci 14.1 on end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 14.3 off end # Camera - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on # PCI Express Port 5 + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on end + device ref south_xdci on end + device ref thermal on end + device ref heci1 on end + device ref sata on end + device ref pcie_rp3 on end + device ref pcie_rp5 on smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" end - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp6 on end + device ref pcie_rp9 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "SSD_M.2 2242/2280" "SlotDataBusWidth4X" end - device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 - device pci 1e.6 off end # SDXC - device pci 1f.0 on + device ref pcie_rp10 on end + device ref pcie_rp11 on end + device ref pcie_rp12 on end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -266,12 +254,9 @@ chip soc/intel/skylake irq 0x70 = 4 end end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end end end |