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authorPatrick Rudolph <patrick.rudolph@9elements.com>2023-10-07 08:03:30 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-11-13 20:43:48 +0000
commite2ce52f59f55791ac3e50457e221931a44929180 (patch)
tree751ebff11b8e3d61f589df09b38907eda550335f /src
parentc3ec144c103f92190af8816bae084c8002aa89ab (diff)
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mb/lenovo/x220: Update devicetree
- Disable unconnected PCH PCIe ports 1 + 3. - Add smbios_slot_desc to WLAN PCIe port - Add comment for PCIe port 7 that might have a XHCI controller connected (some variants only). Test: Lenovo X220 still boots and all devices are still working fine. The WLAN slot is shown in dmidecode -t 9. Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/x220/devicetree.cb11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index b6736d24129a..866d6c3b4104 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -77,9 +77,12 @@ chip northbridge/intel/sandybridge
end # Intel Gigabit Ethernet
device ref ehci2 on end # USB2 EHCI #2
device ref hda on end # High Definition Audio
- device ref pcie_rp1 on end # PCIe Port #1
- device ref pcie_rp2 on end # PCIe Port #2 (wlan)
- device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp1 off end # PCIe Port #1
+ device ref pcie_rp2 on # PCIe Port #2 (wlan)
+ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort"
+ "WIFI" "SlotDataBusWidth1X"
+ end
+ device ref pcie_rp3 off end # PCIe Port #3
device ref pcie_rp4 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end # PCIe Port #4
@@ -91,7 +94,7 @@ chip northbridge/intel/sandybridge
end
end # PCIe Port #5 (SD)
device ref pcie_rp6 off end # PCIe Port #6
- device ref pcie_rp7 on end # PCIe Port #7
+ device ref pcie_rp7 on end # PCIe Port #7 Optional XHCI controller
device ref pcie_rp8 off end # PCIe Port #8
device ref ehci1 on end # USB2 EHCI #1
device ref pci_bridge off end # PCI bridge