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author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-05-04 10:34:02 +0800 |
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committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-05 07:37:13 +0000 |
commit | 46e1b84fad8d8a11c0d84c094f47ef3fa22f711d (patch) | |
tree | 43582b20e27e4b9b85d1b1c165613d911f027e88 /src | |
parent | 1c920108499a7394bd072a7be380e491eac6fa28 (diff) | |
download | coreboot-46e1b84fad8d8a11c0d84c094f47ef3fa22f711d.tar.gz coreboot-46e1b84fad8d8a11c0d84c094f47ef3fa22f711d.tar.bz2 coreboot-46e1b84fad8d8a11c0d84c094f47ef3fa22f711d.zip |
mb/google/cherry: Add NOR-Flash support
TEST=boot to romstage on MT8195 EVB
Change-Id: I356e6b1cba3c078bf99e056b290476c7179e8ccf
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/cherry/Kconfig | 6 | ||||
-rw-r--r-- | src/mainboard/google/cherry/Makefile.inc | 1 | ||||
-rw-r--r-- | src/mainboard/google/cherry/bootblock.c | 37 |
3 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 8c7c0932454c..bf46532a956f 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -22,4 +22,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string default "Cherry" if BOARD_GOOGLE_CHERRY + +# On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus. +# The number here should be a virtual value as (SPI_BUS_NUMBER + 1). +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 7 endif diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index 4831a3950063..a1aa2fd730b2 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += memlayout.ld +bootblock-y += bootblock.c bootblock-y += chromeos.c verstage-y += memlayout.ld diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c new file mode 100644 index 000000000000..6f61a8282b5b --- /dev/null +++ b/src/mainboard/google/cherry/bootblock.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/mmio.h> +#include <soc/gpio.h> + +struct pad_func { + u8 pin_id; + u8 func; +}; + +#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} + +static void nor_set_gpio_pinmux(void) +{ + const struct pad_func *ptr = NULL; + + /* GPIO 140 ~ 143 */ + struct pad_func nor_pinmux[] = { + PAD_FUNC(SPIM2_CSB, SPINOR_CS), + PAD_FUNC(SPIM2_CLK, SPINOR_CK), + PAD_FUNC(SPIM2_MO, SPINOR_IO0), + PAD_FUNC(SPIM2_MI, SPINOR_IO1), + }; + + ptr = nor_pinmux; + for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) { + gpio_set_pull((gpio_t){.id = ptr[i].pin_id}, + GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); + } +} + +void bootblock_mainboard_init(void) +{ + nor_set_gpio_pinmux(); +} |