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| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:37:30 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:06:52 +0000 |
| commit | 50863daef8ed75c0cb3dfd375e7622c898de5821 (patch) | |
| tree | cbb2dea518524f8c9ce5edca5d57132ca9705086 /src | |
| parent | 0949e739066c3509e05db2b9ed71cefaaa62205f (diff) | |
| download | coreboot-50863daef8ed75c0cb3dfd375e7622c898de5821.tar.gz coreboot-50863daef8ed75c0cb3dfd375e7622c898de5821.tar.bz2 coreboot-50863daef8ed75c0cb3dfd375e7622c898de5821.zip | |
src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
58 files changed, 64 insertions, 64 deletions
diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 6ecdaf491078..c3ba99c9057f 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -127,7 +127,7 @@ chip soc/amd/picasso .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_OFF" register "gpp_clk_config[1]" = "GPP_CLK_OFF" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 6342c29f668a..167c3667ab98 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -118,7 +118,7 @@ chip soc/amd/picasso .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 035bb7015b92..1bc5498e3ca5 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -118,7 +118,7 @@ chip soc/amd/picasso .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 83b6597337c9..93d37dcac03e 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -129,7 +129,7 @@ chip northbridge/intel/sandybridge irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b off end # HWM, front pannel LED + device pnp 2e.b off end # HWM, front panel LED device pnp 2e.d on end # VID device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f on end # GPIO Push-Pull or Open-drain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index a50c2aca3717..ff0503066ca2 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -105,7 +105,7 @@ chip northbridge/intel/x4x # Northbridge irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 io 0x62 = 0x200 irq 0x70 = 0 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 7ceefaabe845..89e6ebb8fcec 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -99,7 +99,7 @@ chip northbridge/intel/x4x # Northbridge device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index e583f7f763d0..c3c6b1b17abd 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -100,7 +100,7 @@ chip northbridge/intel/x4x # Northbridge device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index 48376ff8bdd8..5efb74959f8a 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -34,7 +34,7 @@ chip northbridge/intel/x4x # Northbridge irq 0x70 = 0 irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 78ad87771521..8653cec2c568 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -106,9 +106,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 1, 0x0080 }, /* USB3 ETH bottom connector */ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 5f32d8b7cce6..387a66742474 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -18,7 +18,7 @@ * with -bios option which neatly puts coreboot into flash and so payloads * can find CBFS and we don't risk overwriting CBFS. * - * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash + * Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash * and -bios was unusable as $pc pointed to 0 which was zero-filled as a * workaround we suggested using -kernel but this still had all the issues * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index a239590e1e66..e972f5426184 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -2,7 +2,7 @@ /* * These are the qemu firmware config interface defines and structs. - * Copied over from qemu soure tree, + * Copied over from qemu source tree, * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly. */ #ifndef FW_CFG_IF_H diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 4a9a52fb4212..ec86c70a3c85 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -16,7 +16,7 @@ static void bootblock_northbridge_init(void) * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index be995731ecba..cdd34a464e36 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -181,7 +181,7 @@ static const struct edp_data b101uan08_table[] = { {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, - /* Additional Settng for eDP */ + /* Additional Setting for eDP */ {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} }, {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} }, /* DPRX CAD Register Setting */ diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901c65..5a81678f1f79 100644 --- a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26c9a15..f0dc7fb0d7c2 100644 --- a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6f8eb7..2a03e0480fa6 100644 --- a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 1df786db83c1..8e2bbe8a255e 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -202,7 +202,7 @@ static void setup_storage(void) static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c0(); exynos_pinmux_i2c1(); exynos_pinmux_i2c2(); @@ -222,7 +222,7 @@ static void gpio_init(void) gpio_direction_output(GPIO_X17, 1); gpio_direction_output(GPIO_X15, 1); - /* Set up the I2S busses. */ + /* Set up the I2S buses. */ exynos_pinmux_i2s0(); exynos_pinmux_i2s1(); } diff --git a/src/mainboard/google/foster/bct/jtag.cfg b/src/mainboard/google/foster/bct/jtag.cfg index e9bbd024a572..58186b237799 100644 --- a/src/mainboard/google/foster/bct/jtag.cfg +++ b/src/mainboard/google/foster/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set DebugCtrl to 1 to reenable Jtag +# Set DebugCtrl to 1 to re-enable Jtag # DebugCtrl = 0; # diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 5dddab5584d8..3aafa9eeeb99 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -60,7 +60,7 @@ int pwm_enum_to_pwm_number[] = { void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; - int voltage = millivolt * 10; /* for higer calculation accuracy */ + int voltage = millivolt * 10; /* for higher calculation accuracy */ int pwm_number = pwm_enum_to_pwm_number[pwm]; voltage_min = pwm_design_voltage[pwm][0]; diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 260e9340bd8f..381cbaaab81f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -80,7 +80,7 @@ chip soc/amd/cezanne register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f78d42096d3d..a84eabde5c7e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/cannonlake register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" - # SD card WP pin confguration + # SD card WP pin configuration register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 59c49590a36d..ffec6a5396bd 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -117,7 +117,7 @@ static void mainboard_init(void *chip_info) gpios = variant_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); - /* Initialize i2c busses that were not initialized in bootblock */ + /* Initialize i2c buses that were not initialized in bootblock */ i2c_soc_init(); /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 1816dafc4aa4..728487a4316a 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -7,7 +7,7 @@ static void prepare_usb(void) { /* * Do DWC3 core and phy reset. Kick these resets off early - * so they get atleast 1msec to settle. + * so they get at least 1msec to settle. */ reset_usb(HSUSB_HS_PORT_1); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 0e9dc1359c4a..afbea9c77004 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -231,7 +231,7 @@ static void display_startup(void) static void mainboard_init(struct device *dev) { /* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which - * also contains the PS8640 eDP brige and the USB hub. + * also contains the PS8640 eDP bridge and the USB hub. */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) mt6391_gpio_output(MT6391_KP_ROW2, 1); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 65bf286f08ab..9ffd63373868 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -69,7 +69,7 @@ static void gpio_modification_by_ssfc(struct pad_config *table, size_t num) /* * Currently we only have the case of RT5682 as the second source. And * in case of Ampton which used RT5682 as the default source, it didn't - * provide override_table right now so it will be returned ealier since + * provide override_table right now so it will be returned earlier since * table above is NULL. */ if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 85b0cc0afc62..6878cadf972d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -324,7 +324,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index e6b835999662..63763b34aaa7 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index c279777e47fd..9cefb81bf85c 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -330,7 +330,7 @@ static void setup_storage(void) static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c2(); exynos_pinmux_i2c4(); exynos_pinmux_i2c7(); diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 4b1254da9583..d588d575dc1e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -262,7 +262,7 @@ Scope (\_SB.PCI0.I2C2) * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/google/smaug/bct/jtag.cfg b/src/mainboard/google/smaug/bct/jtag.cfg index 4f2c36c22315..c48e54a19188 100644 --- a/src/mainboard/google/smaug/bct/jtag.cfg +++ b/src/mainboard/google/smaug/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set JtagCtrl to 1 to reenable Jtag +# Set JtagCtrl to 1 to re-enable Jtag # JtagCtrl = 0; # diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 8e2d8590a69f..89958c92565b 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal handeler + // Thermal handler #include "acpi/thermal.asl" // global NVS and variables diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 947672373507..68eb6ea5887e 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -232,7 +232,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ce0121593bb3..4bb42dea1c97 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -19,7 +19,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -230,7 +230,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_OFF" diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 43ae7150ddfb..3f7e5d1c340d 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -49,7 +49,7 @@ void variant_touchscreen_update(void); void variant_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and - * overrideable by the variant. */ + * overridable by the variant. */ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 389b44e1e190..f7821d0e98be 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -81,7 +81,7 @@ chip northbridge/intel/sandybridge device pnp 4e.609 off end # GPIO6 device pnp 4e.709 off end # GPIO7 device pnp 4e.a on end # ACPI - device pnp 4e.b on # HWM, front pannel LED + device pnp 4e.b on # HWM, front panel LED io 0x60 = 0xa30 io 0x62 = 0 # unused end diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 9b1aeb025297..5f945c1c3376 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -129,7 +129,7 @@ chip northbridge/intel/x4x # Northbridge irq 0xe4 = 0x10 # Power dram during s3 irq 0xe6 = 0x8c end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0xa00 irq 0x70 = 0 end diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index 26108a2592ad..0d1158dd370f 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -108,7 +108,7 @@ Scope (\_SB.PCI0.I2C2) * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) @@ -613,7 +613,7 @@ Scope (\_SB.PCI0.I2C3) * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index 4d4b5789d3b3..3f420c0d344d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -104,7 +104,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /** - * @brief Customer Overides Memory Table + * @brief Customer Overrides Memory Table * * Platform Specific Overriding Table allows IBV/OEM to pass in platform * information to AGESA diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 7365d7482532..22c88e0c49c2 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -144,7 +144,7 @@ Device (EC0) ^HKEY.MHKQ (0x6040) } - /* Lid openend */ + /* Lid opened */ Method (_Q2A, 0, NotSerialized) { LIDS = 1 diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 5d1e2613ba69..e35a70b8ae1d 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -535,7 +535,7 @@ DefinitionBlock ( * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901c65..5a81678f1f79 100644 --- a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26c9a15..f0dc7fb0d7c2 100644 --- a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6f8eb7..2a03e0480fa6 100644 --- a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c index 074535258205..33519b9d4249 100644 --- a/src/mainboard/protectli/vault_bsw/romstage.c +++ b/src/mainboard/protectli/vault_bsw/romstage.c @@ -12,7 +12,7 @@ void mainboard_after_memory_init(void) { /* - * FSP enables internal UART. Disable it and reenable Super I/O UART to + * FSP enables internal UART. Disable it and re-enable Super I/O UART to * prevent loss of debug information on serial. */ pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 72eaca4bebd6..73255623073e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -32,7 +32,7 @@ Device (EC) BIF0, 16, BDCP, 16, // BAT Design Capacity BFCP, 16, // BAT Full Capacity - BRCH, 16, // BAT Rechargable + BRCH, 16, // BAT Rechargeable BDVT, 16, // BAT Design Voltage BIF5, 16, BIF6, 16, diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index 720f92f97479..fbe4173cb74c 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -42,7 +42,7 @@ Device(EC0) FDDI, 1, // floppy on lpt indicator? LIDC, 1, // LID switch Offset(0xd0), - TCPU, 8, // T_CPU in deg Celcius + TCPU, 8, // T_CPU in deg Celsius Offset(0xd6), /* exact purpose of these three is guessed, but it's something about cooling */ diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 907edc1adf3c..5c2984689158 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -4,7 +4,7 @@ Scope (\_TZ) { - /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + /* degree Celsius to deci-Kelvin (ACPI temperature unit) */ Method(C2dK, 1) { Add (2732, Multiply (Arg0, 10), Local0) Return (Local0) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 02799d3f1183..23220976dd9d 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,7 @@ static const char *northbridge_acpi_name(const struct device *dev) } /* - * TODO: We could determine how many PCIe busses we need in the bar. + * TODO: We could determine how many PCIe buses we need in the bar. * For now, that number is hardcoded to a max of 64. */ static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 51ee32034290..ac19fccfc8a6 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -63,7 +63,7 @@ config MAXIMUM_SUPPORTED_FREQUENCY config CHECK_SLFRCS_ON_RESUME def_bool n help - On some boards it may be neccessary to hard reset early + On some boards it may be necessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 6610a3e38c9c..241eb430212c 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -22,7 +22,7 @@ void bootblock_early_northbridge_init(void) { /* * The QuickPath bus number is the topmost bus number, as per the value - * of the SAD_PCIEXBAR register. The register defaults to 256 busses on + * of the SAD_PCIEXBAR register. The register defaults to 256 buses on * reset. Thus, hardcode the bus number when first setting up PCIEXBAR. */ const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4b5f2b3a242a..9ef491baedb5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2437,7 +2437,7 @@ int aggressive_write_training(ramctr_timing *ctrl) if (enable_iosav_opt) mchbar_write32(MCMNTS_SPARE, 1); - printram("Aggresive write training:\n"); + printram("Aggressive write training:\n"); for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { FOR_ALL_POPULATED_CHANNELS { diff --git a/src/security/intel/cbnt/logging.c b/src/security/intel/cbnt/logging.c index 55354b4ce8cd..514e5ac66602 100644 --- a/src/security/intel/cbnt/logging.c +++ b/src/security/intel/cbnt/logging.c @@ -123,7 +123,7 @@ void intel_cbnt_log_registers(void) LOG("SACM INFO MSR (0x13A) raw: 0x%016llx\n", acm_info.raw); LOG(" NEM status: %u\n", acm_info.nem_enabled); LOG(" TPM type: %s\n", tpm_type[acm_info.tpm_type]); - LOG(" TPM succes: %u\n", acm_info.tpm_success); + LOG(" TPM success: %u\n", acm_info.tpm_success); LOG(" FACB: %u\n", acm_info.facb); LOG(" measured boot: %u\n", acm_info.measured_boot); LOG(" verified boot: %u\n", acm_info.verified_boot); diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index e2fab0c063fc..1ebe77d2f1a3 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -668,7 +668,7 @@ bool stm_check_stm_image(void *stm_image, uint32_t stm_imagesize) /* * This function return BIOS STM resource. * Produced by SmmStm. - * Comsumed by SmmMpService when Init. + * Consumed by SmmMpService when Init. * * @return BIOS STM resource */ diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 2b7d92627c52..e3e2f5c46952 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -150,7 +150,7 @@ static struct acm_info_table *find_info_table(const void *ptr) } /** - * Validate that the provided ACM is useable on this platform. + * Validate that the provided ACM is usable on this platform. */ static int validate_acm(const void *ptr) { diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 557125dcf810..03c6f8bd75a9 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -98,7 +98,7 @@ static void clear_memory(void *unused) __func__, (void *)pgtbl, (void *)vmem_addr); } - /* Now clear all useable DRAM */ + /* Now clear all usable DRAM */ memranges_each_entry(r, &mem) { if (range_entry_tag(r) != BM_MEM_RAM) continue; diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index e040d8061162..ed642c33b59f 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -55,7 +55,7 @@ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, const char *name); /** - * Issue a TPM_Clear and reenable/reactivate the TPM. + * Issue a TPM_Clear and re-enable/reactivate the TPM. * @return TPM_SUCCESS on success. If not a tpm error is returned */ uint32_t tpm_clear_and_reenable(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index f464fe19e7f6..cfa533b880cb 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -273,7 +273,7 @@ uint32_t tlcl_self_test_full(void) uint32_t tlcl_lock_nv_write(uint32_t index) { struct tpm2_response *response; - /* TPM Wll reject attempts to write at non-defined index. */ + /* TPM Will reject attempts to write at non-defined index. */ struct tpm2_nv_write_lock_cmd nv_wl = { .nvIndex = HR_NV_INDEX + index, }; @@ -372,7 +372,7 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size, if (!response) return TPM_E_NO_DEVICE; - /* Map TPM2 retrun codes into common vboot represenation. */ + /* Map TPM2 return codes into common vboot representation. */ switch (response->hdr.tpm_code) { case TPM2_RC_SUCCESS: return TPM_SUCCESS; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index ae0b7fdca53c..3ae48eb48432 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -28,7 +28,7 @@ int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, * tpm_unmarshal_response * * Given a buffer received from the TPM in response to a certain command, - * deserialize the buffer into the expeced response structure. + * deserialize the buffer into the expected response structure. * * struct tpm2_response is a union of all possible responses. * |