diff options
| author | John Zhao <john.zhao@intel.com> | 2021-04-21 10:48:20 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-23 14:48:04 +0000 |
| commit | a66b816675fc299e03092ef8d7b2c59f04641fb7 (patch) | |
| tree | 5f561621e203d0375610c33e1e0f8991877ff808 /src | |
| parent | eb2a784b8b9d51b559246c5f7c65cae7163ddb08 (diff) | |
| download | coreboot-a66b816675fc299e03092ef8d7b2c59f04641fb7.tar.gz coreboot-a66b816675fc299e03092ef8d7b2c59f04641fb7.tar.bz2 coreboot-a66b816675fc299e03092ef8d7b2c59f04641fb7.zip | |
soc/intel/jasperlake: Remove TCSS setting from the DMAR table
The Jasperlake does not support TCSS. This change removes the TCSS
setting from the DMAR table.
BUG=None
TEST=Built image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I573e2038fd76ac66af88125117774b40cc80c704
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52575
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/jasperlake/acpi.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/iomap.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/systemagent.h | 10 |
3 files changed, 0 insertions, 36 deletions
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index ebfa6685fe33..f73766a8d778 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -216,20 +216,6 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - /* TCSS Thunderbolt root ports */ - for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { - uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK; - bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED; - if (tbtbar && tbten) { - unsigned long tmp = current; - - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); - current += acpi_create_dmar_ds_pci(current, 0, 7, i); - - acpi_dmar_drhd_fixup(tmp, current); - } - } - /* Add RMRR entry */ const unsigned long tmp = current; current += acpi_create_dmar_rmrr(current, 0, diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index eece24aa96fa..a6ac8367a3b2 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -29,18 +29,6 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 -#define TBT0_BASE_ADDRESS 0xfed84000 -#define TBT0_BASE_SIZE 0x1000 - -#define TBT1_BASE_ADDRESS 0xfed85000 -#define TBT1_BASE_SIZE 0x1000 - -#define TBT2_BASE_ADDRESS 0xfed86000 -#define TBT2_BASE_SIZE 0x1000 - -#define TBT3_BASE_ADDRESS 0xfed87000 -#define TBT3_BASE_SIZE 0x1000 - #define GFXVT_BASE_ADDRESS 0xfed90000 #define GFXVT_BASE_SIZE 0x1000 diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index 6acd7f3e4b37..d6f41257a5bc 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -24,12 +24,6 @@ #define IMRBASE 0x6a40 #define IMRLIMIT 0x6a48 #define IPUVTBAR 0x7880 -#define TBT0BAR 0x7888 -#define TBT1BAR 0x7890 -#define TBT2BAR 0x7898 -#define TBT3BAR 0x78a0 - -#define MAX_TBT_PCIE_PORT 4 #define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull @@ -37,10 +31,6 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = { { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, }; |