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| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-04-15 16:25:49 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-23 14:52:14 +0000 |
| commit | b20d69462280761ff885177cc925c8126744a082 (patch) | |
| tree | 213d2985f51cd07171e4b909e4133f44fe35a009 /src | |
| parent | 456b7ba842e05348a8349c81b52d18faae9e42d6 (diff) | |
| download | coreboot-b20d69462280761ff885177cc925c8126744a082.tar.gz coreboot-b20d69462280761ff885177cc925c8126744a082.tar.bz2 coreboot-b20d69462280761ff885177cc925c8126744a082.zip | |
soc/intel/xeon_sp/cpx: Add UPI locks
Add UPI locks as indicated by the Intel docs.
Change-Id: I9d1336e57f1776f3024883d6edcf0a855b1382c6
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 6 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index f4a9e8282b5f..3eaf46f1cf63 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -167,6 +167,13 @@ static void set_imc_locks(void) pci_or_config32(dev, IMC_M2MEM_TIMEOUT, TIMEOUT_LOCK); } +static void set_upi_locks(void) +{ + struct device *dev = 0; + while ((dev = dev_find_device(PCI_VENDOR_ID_INTEL, UPI_LL_CR_DEVID, dev))) + pci_or_config32(dev, UPI_LL_CR_KTIMISCMODLCK, KTIMISCMODLCK_LOCK); +} + static void chip_final(void *data) { /* Lock SBI */ @@ -186,6 +193,7 @@ static void chip_final(void *data) mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); set_imc_locks(); + set_upi_locks(); p2sb_hide(); iio_enable_masks(); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 0f9a1c31fbe4..ef918c6d005e 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -124,6 +124,12 @@ #define IMC_M2MEM_TIMEOUT 0x104 #define TIMEOUT_LOCK BIT(1) +/* UPI Devices */ +/* Bus: B(3), Device: 16,14, Function: 3 (LL_CR) */ +#define UPI_LL_CR_DEVID 0x205B +#define UPI_LL_CR_KTIMISCMODLCK 0x300 +#define KTIMISCMODLCK_LOCK BIT(0) + /* CPU Devices */ #define CBDMA_DEV_NUM 0x04 |