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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-04-22 17:03:56 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:28:36 +0000 |
| commit | b6a4476f342afa0b65f15b2f225d2e1dc3b3c776 (patch) | |
| tree | eb360856fb886cda218ad3ba744a6a521869cdea /src | |
| parent | 5ad85d95cd656996acbfef5c8bea791662b551cd (diff) | |
| download | coreboot-b6a4476f342afa0b65f15b2f225d2e1dc3b3c776.tar.gz coreboot-b6a4476f342afa0b65f15b2f225d2e1dc3b3c776.tar.bz2 coreboot-b6a4476f342afa0b65f15b2f225d2e1dc3b3c776.zip | |
mb/google/guybrush: Enable S0i3
BUG=b:185939089
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 84bdfcf206fa..305dfbfc6f3e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -38,6 +38,9 @@ chip soc/amd/cezanne .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), }" + # Enable S0i3 support + register "s0ix_enable" = "1" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" |