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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-11 02:43:07 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-02-12 20:49:10 +0000 |
| commit | 34fc29ae96d2ae6e0d021c84fc3ff8d56ec38898 (patch) | |
| tree | 972a40dc74d75f5c99d628ff62c2422e352e9caf /src | |
| parent | 1b33205909c5a8f775eefd19107406a620a7fcc5 (diff) | |
| download | coreboot-34fc29ae96d2ae6e0d021c84fc3ff8d56ec38898.tar.gz coreboot-34fc29ae96d2ae6e0d021c84fc3ff8d56ec38898.tar.bz2 coreboot-34fc29ae96d2ae6e0d021c84fc3ff8d56ec38898.zip | |
soc/amd: add and use fch_enable_hpet_decode
On Picasso we missed setting this bit in coreboot and since the default
after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge
and Cezanne have the HPET decode enable bit in the same position in the
same register. In the ACPI table entry written by
southbridge_write_acpi_tables the HPET entry gets added, so we should
make sure that we enable the decode.
TEST=HPET still works on Mandolin.
Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/acpimmio/mmio_util.c | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/acpimmio.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/smbus/sm.c | 1 |
3 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index a19a28bd0e3d..3a86aafbb544 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -79,6 +79,14 @@ void fch_enable_ioapic_decode(void) pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | FCH_IOAPIC_EN); } +void fch_configure_hpet(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + reg |= HPET_EN | HPET_MSI_EN; + reg &= ~HPET_WIDTH_SEL; /* 32 bit HPET */ + pm_write32(PM_DECODE_EN, reg); +} + /* PM registers are accessed a byte at a time via CD6/CD7 */ uint8_t pm_io_read8(uint8_t reg) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 19decdd81bd9..a9a6986c77ec 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -15,8 +15,11 @@ * newer SoCs, but not for the generations with separate FCH or Kabini. */ #define PM_DECODE_EN 0x00 +#define HPET_MSI_EN (1 << 29) +#define HPET_WIDTH_SEL (1 << 28) /* 0=32bit, 1=64bit */ #define SMBUS_ASF_IO_BASE_SHIFT 8 #define SMBUS_ASF_IO_BASE_MASK (0xff << SMBUS_ASF_IO_BASE_SHIFT) +#define HPET_EN (1 << 6) /* decode HPET MMIO at 0xfed00000 */ #define FCH_IOAPIC_EN (1 << 5) #define SMBUS_ASF_IO_EN (1 << 4) #define CF9_IO_EN (1 << 1) @@ -77,6 +80,7 @@ void fch_enable_cf9_io(void); void fch_enable_legacy_io(void); void fch_io_enable_legacy_io(void); void fch_enable_ioapic_decode(void); +void fch_configure_hpet(void); /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 0b219e006d52..b1b3db6192c7 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -13,6 +13,7 @@ static void sm_init(struct device *dev) { fch_enable_ioapic_decode(); setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); + fch_configure_hpet(); } static u32 get_sm_mmio(struct device *dev) |