AGESA f14/f15tn/f16kb: Clean up buildOpts.c files

Until now, the buildOpts.c files were primarily made out of copy-pasted
AGESA options, commented-out definitions and several useless comments;
that is, the materialization of technical debt in GCC-parsable form...

Until now.

It is assumed that the boards in the tree still boot. So, by comparing
their settings, we can extract saner defaults to place into AGESA. Many
of the settings were common across all boards of the same family, so we
promote those values to default settings. In some cases flipping a flag
was required, so the macros to alter that option had to be adapted as
well. Since those AGESA versions are expected to never receive updates,
it should not be a problem to change their files to suit our needs.

As a result, all but two buildOpts.c files now have less than 100 lines.
AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require
about 60 or 70 lines in those files. Hopefully, this will make porting
more mainboards using AGESA f14/f15tn/f16kb a substantially easier task.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>

33 files changed, 809 insertions, 5023 deletions

diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index aecc9a5b08f6..73216349ce66 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -1,160 +1,32 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-/* Select the CPU socket type. */
+/* Select the CPU socket type */
 #define INSTALL_FT1_SOCKET_SUPPORT		TRUE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
+/* Agesa optional capabilities selection */
 #define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
 #define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
 #define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE		TRUE
 #define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE		TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING		FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING		FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT	TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT	TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES		FALSE
-#define BLDCFG_REMOVE_ACPI_PSTATES_PPC		FALSE
-#define BLDCFG_REMOVE_ACPI_PSTATES_PCT		FALSE
-#define BLDCFG_REMOVE_ACPI_PSTATES_PSD		FALSE
-#define BLDCFG_REMOVE_ACPI_PSTATES_PSS		FALSE
-#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS		FALSE
-#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT	FALSE
-#define BLDOPT_REMOVE_SRAT			FALSE
-#define BLDOPT_REMOVE_SLIT			FALSE
 #define BLDOPT_REMOVE_WHEA			FALSE
-#define BLDOPT_REMOVE_DMI			TRUE
-#define BLDOPT_REMOVE_HT_ASSIST			TRUE
-#define BLDOPT_REMOVE_ATM_MODE			TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E		TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT	FALSE
-//#define BLDOPT_REMOVE_C6_STATE		TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY		TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES		TRUE
 
-#define BLDCFG_VRM_CURRENT_LIMIT		24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT		0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD		24000
 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-#define BLDCFG_VRM_SLEW_RATE			5000
-//#define BLDCFG_VRM_NB_SLEW_RATE		5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY		0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY	0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE		TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE	FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT		6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
 
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0		'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1		'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB		FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS		3
-//#define BLDCFG_PLATFORM_C1E_MODE		C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1	0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2	0
-#define BLDCFG_PLATFORM_CSTATE_MODE		CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA		0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE		CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE		CORE_LEVEL_LOWEST
 #define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM		0
-//#define BLDCFG_MAXIMUM_BUSNUM			0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS		0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST	0
-//#define BLDCFG_BUID_SWAP_LIST			0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST		0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST		0
-//#define BLDCFG_BUS_NUMBERS_LIST		0
-//#define BLDCFG_IGNORE_LINK_LIST		0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST		0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST	0
-//#define BLDCFG_USE_HT_ASSIST			TRUE
-//#define BLDCFG_USE_ATM_MODE			TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE	Nfcm
 #define BLDCFG_S3_LATE_RESTORE			FALSE
-//#define BLDCFG_USE_32_BYTE_REFRESH		FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE	Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD		FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING		FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP	0
 #define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-//#define BLDCFG_CFG_ABM_SUPPORT		FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE	0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL	0
-//#define BLDCFG_MEM_INIT_PSTATE		0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE		0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT	DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED		TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE	TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE		QUADRANK_UNBUFFERED
 #define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
 #define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_POWER_DOWN		TRUE
-#define BLDCFG_POWER_DOWN_MODE			POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE			FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE		FALSE
-#define BLDCFG_BANK_SWIZZLE			TRUE
-#define BLDCFG_TIMING_MODE_SELECT		TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT		DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL		TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM		FALSE
-#define BLDCFG_USE_BURST_MODE			FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON		FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
-//#define BLDCFG_ECC_REDIRECTION		FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE		0
-//#define BLDCFG_SCRUB_L2_RATE			0
-//#define BLDCFG_SCRUB_L3_RATE			0
-//#define BLDCFG_SCRUB_IC_RATE			0
-//#define BLDCFG_SCRUB_DC_RATE			0
-//#define BLDCFG_ECC_SYNC_FLOOD			0
-//#define BLDCFG_ECC_SYMBOL_SIZE		0
-//#define BLDCFG_1GB_ALIGN			FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE		UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE		0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT		FALSE
-#define BLDCFG_UMA_ALIGNMENT			NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS		0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
 
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +39,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index f5ac7427278e..0e09739f03df 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -1,196 +1,34 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
-
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
 
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                  15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
+#define BLDOPT_REMOVE_CDIT			TRUE
 
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+/* Build configuration values here. */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			TRUE
 
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -205,54 +43,4 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   olivehill_gpio[] = {
-	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
-	{-1}
-};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&olivehill_gpio[0])
-
 #include <PlatformInstall.h>
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 694eda7a1b55..5ab39a13b2f9 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -1,198 +1,38 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_10_SUPPORT FALSE
-#define INSTALL_FAMILY_12_SUPPORT FALSE
-#define INSTALL_FAMILY_14_SUPPORT FALSE
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  TRUE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  TRUE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+/* Select the CPU family */
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
 
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+/* Select the CPU socket type */
+#define INSTALL_FS1_SOCKET_SUPPORT		TRUE
+#define INSTALL_FP2_SOCKET_SUPPORT		TRUE
 
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 90000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM        36		// PCIE Spread Spectrum default value 0.36%
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770
 
-#define BLDOPT_REMOVE_ALIB                    FALSE
-#define BLDCFG_PLATFORM_CPB_MODE                  CpbModeDisabled
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
+/* Build configuration values here. */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         200
-#define BLDCFG_CFG_ABM_SUPPORT                    0
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
 
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+#define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
 
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Trinity
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               60000
-
-#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON	3
-#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL	3
-
-#if CONFIG(GFXUMA)
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE		  UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE		  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */
-#define BLDCFG_UMA_ALLOCATION_SIZE		  0x2000//512M
-#define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE
-#endif
-
-#define BLDCFG_IOMMU_SUPPORT    FALSE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -207,54 +47,10 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   parmer_gpio[] = {
+GPIO_CONTROL parmer_gpio[] = {
 	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&parmer_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(parmer_gpio)
 
 #include <PlatformInstall.h>
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 91c2182361d3..d8d46d499e6f 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -1,160 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
 
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
 
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						FALSE
-#define BLDOPT_REMOVE_SLIT						FALSE
-#define BLDOPT_REMOVE_WHEA						FALSE
-#define BLDOPT_REMOVE_DMI						TRUE
-#define BLDOPT_REMOVE_HT_ASSIST					TRUE
-#define BLDOPT_REMOVE_ATM_MODE					TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_C6_STATE				TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
 
-#define BLDCFG_VRM_CURRENT_LIMIT				24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
-#define BLDCFG_VRM_SLEW_RATE					5000
-//#define BLDCFG_VRM_NB_SLEW_RATE				5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS				3
-//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA			0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
-#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM				0
-//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
-//#define BLDCFG_BUID_SWAP_LIST					0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
-//#define BLDCFG_BUS_NUMBERS_LIST				0
-//#define BLDCFG_IGNORE_LINK_LIST				0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
-//#define BLDCFG_USE_HT_ASSIST					TRUE
-//#define BLDCFG_USE_ATM_MODE					TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
-#define BLDCFG_S3_LATE_RESTORE					TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
-#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
-//#define BLDCFG_MEM_INIT_PSTATE				0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
-#define BLDCFG_MEMORY_POWER_DOWN				TRUE
-#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE					FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
-#define BLDCFG_BANK_SWIZZLE						TRUE
-#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
-#define BLDCFG_USE_BURST_MODE					FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
-//#define BLDCFG_ECC_REDIRECTION				FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE				0
-//#define BLDCFG_SCRUB_L2_RATE					0
-//#define BLDCFG_SCRUB_L3_RATE					0
-//#define BLDCFG_SCRUB_IC_RATE					0
-//#define BLDCFG_SCRUB_DC_RATE					0
-//#define BLDCFG_ECC_SYNC_FLOOD					0
-//#define BLDCFG_ECC_SYMBOL_SIZE				0
-//#define BLDCFG_1GB_ALIGN						FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE				UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE				0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
-#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +38,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 44248a25e5b2..453102aa6a25 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -1,160 +1,32 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT  TRUE
-
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
-  #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-#define BLDOPT_REMOVE_SRAT            TRUE
-#define BLDOPT_REMOVE_SLIT            TRUE
-#define BLDOPT_REMOVE_WHEA            TRUE
-#define BLDOPT_REMOVE_DMI             TRUE
-#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-#define BLDOPT_REMOVE_ATM_MODE          TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
-//#define BLDOPT_REMOVE_C6_STATE          TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
-
-#define BLDCFG_VRM_CURRENT_LIMIT                24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT             0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD          24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD       1
-#define BLDCFG_VRM_SLEW_RATE                    5000
-//#define BLDCFG_VRM_NB_SLEW_RATE                 5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY             0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY          0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE            TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE         FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT         6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT      0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0            'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1            '0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB            FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS                3
-//#define BLDCFG_PLATFORM_C1E_MODE                C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA              0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
-#define BLDCFG_PLATFORM_CSTATE_MODE             CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA           0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
-//#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM                  0
-//#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS                0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST         0
-//#define BLDCFG_BUID_SWAP_LIST                   0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST  0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST             0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST              0
-//#define BLDCFG_BUS_NUMBERS_LIST                 0
-//#define BLDCFG_IGNORE_LINK_LIST                 0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST            0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST       0
-//#define BLDCFG_USE_HT_ASSIST                    TRUE
-//#define BLDCFG_USE_ATM_MODE                     TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE       Nfcm
-#define BLDCFG_S3_LATE_RESTORE                    FALSE
-//#define BLDCFG_USE_32_BYTE_REFRESH              FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY   FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE       Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD             FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING             FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP       0
-#define BLDCFG_CFG_GNB_HD_AUDIO                 TRUE
-//#define BLDCFG_CFG_ABM_SUPPORT                  FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE         0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL       0
-//#define BLDCFG_MEM_INIT_PSTATE                  0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE             0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT       DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED             TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE         TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE             QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE            TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE            FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING      FALSE
-#define BLDCFG_MEMORY_POWER_DOWN                TRUE
-#define BLDCFG_POWER_DOWN_MODE                  POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE                     FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE             FALSE
-#define BLDCFG_BANK_SWIZZLE                     TRUE
-#define BLDCFG_TIMING_MODE_SELECT               TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT              DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL             TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM              FALSE
-#define BLDCFG_USE_BURST_MODE                   FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON             FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE               TRUE
-//#define BLDCFG_ECC_REDIRECTION                  FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE                  0
-//#define BLDCFG_SCRUB_L2_RATE                    0
-//#define BLDCFG_SCRUB_L3_RATE                    0
-//#define BLDCFG_SCRUB_IC_RATE                    0
-//#define BLDCFG_SCRUB_DC_RATE                    0
-//#define BLDCFG_ECC_SYNC_FLOOD                   0
-//#define BLDCFG_ECC_SYMBOL_SIZE                  0
-//#define BLDCFG_1GB_ALIGN                        FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE              UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE              0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT              FALSE
-#define BLDCFG_UMA_ALIGNMENT                    NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
+
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
+
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			TRUE
+
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
+
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_S3_LATE_RESTORE			FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
+
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +39,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index f9908ef3092e..433a9f428e9e 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -1,198 +1,38 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_10_SUPPORT FALSE
-#define INSTALL_FAMILY_12_SUPPORT FALSE
-#define INSTALL_FAMILY_14_SUPPORT FALSE
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  TRUE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  TRUE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+/* Select the CPU family */
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
 
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+/* Select the CPU socket type */
+#define INSTALL_FS1_SOCKET_SUPPORT		TRUE
+#define INSTALL_FP2_SOCKET_SUPPORT		TRUE
 
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 90000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM        36		// PCIE Spread Spectrum default value 0.36%
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770
 
-#define BLDOPT_REMOVE_ALIB                    FALSE
-#define BLDCFG_PLATFORM_CPB_MODE                  CpbModeDisabled
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
+/* Build configuration values here. */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         200
-#define BLDCFG_CFG_ABM_SUPPORT                    0
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
 
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+#define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
 
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Trinity
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               60000
-
-#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON	3
-#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL	3
-
-#if CONFIG(GFXUMA)
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE		  UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE      	  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */
-#define BLDCFG_UMA_ALLOCATION_SIZE      	  0x2000//512M
-#define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE
-#endif
-
-#define BLDCFG_IOMMU_SUPPORT    FALSE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -207,54 +47,12 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
 #define FCH_NO_XHCI_SUPPORT			TRUE
-GPIO_CONTROL   thatcher_gpio[] = {
+
+GPIO_CONTROL thatcher_gpio[] = {
 	{183, Function1, PullUpB},
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&thatcher_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(thatcher_gpio)
 
 #include <PlatformInstall.h>
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 44248a25e5b2..453102aa6a25 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -1,160 +1,32 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT  TRUE
-
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
-  #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-#define BLDOPT_REMOVE_SRAT            TRUE
-#define BLDOPT_REMOVE_SLIT            TRUE
-#define BLDOPT_REMOVE_WHEA            TRUE
-#define BLDOPT_REMOVE_DMI             TRUE
-#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-#define BLDOPT_REMOVE_ATM_MODE          TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
-//#define BLDOPT_REMOVE_C6_STATE          TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
-
-#define BLDCFG_VRM_CURRENT_LIMIT                24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT             0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD          24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD       1
-#define BLDCFG_VRM_SLEW_RATE                    5000
-//#define BLDCFG_VRM_NB_SLEW_RATE                 5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY             0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY          0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE            TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE         FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT         6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT      0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0            'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1            '0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB            FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS                3
-//#define BLDCFG_PLATFORM_C1E_MODE                C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA              0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
-#define BLDCFG_PLATFORM_CSTATE_MODE             CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA           0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
-//#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM                  0
-//#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS                0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST         0
-//#define BLDCFG_BUID_SWAP_LIST                   0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST  0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST             0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST              0
-//#define BLDCFG_BUS_NUMBERS_LIST                 0
-//#define BLDCFG_IGNORE_LINK_LIST                 0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST            0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST       0
-//#define BLDCFG_USE_HT_ASSIST                    TRUE
-//#define BLDCFG_USE_ATM_MODE                     TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE       Nfcm
-#define BLDCFG_S3_LATE_RESTORE                    FALSE
-//#define BLDCFG_USE_32_BYTE_REFRESH              FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY   FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE       Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD             FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING             FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP       0
-#define BLDCFG_CFG_GNB_HD_AUDIO                 TRUE
-//#define BLDCFG_CFG_ABM_SUPPORT                  FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE         0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL       0
-//#define BLDCFG_MEM_INIT_PSTATE                  0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE             0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT       DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED             TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE         TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE             QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE            TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE            FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING      FALSE
-#define BLDCFG_MEMORY_POWER_DOWN                TRUE
-#define BLDCFG_POWER_DOWN_MODE                  POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE                     FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE             FALSE
-#define BLDCFG_BANK_SWIZZLE                     TRUE
-#define BLDCFG_TIMING_MODE_SELECT               TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT              DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL             TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM              FALSE
-#define BLDCFG_USE_BURST_MODE                   FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON             FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE               TRUE
-//#define BLDCFG_ECC_REDIRECTION                  FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE                  0
-//#define BLDCFG_SCRUB_L2_RATE                    0
-//#define BLDCFG_SCRUB_L3_RATE                    0
-//#define BLDCFG_SCRUB_IC_RATE                    0
-//#define BLDCFG_SCRUB_DC_RATE                    0
-//#define BLDCFG_ECC_SYNC_FLOOD                   0
-//#define BLDCFG_ECC_SYMBOL_SIZE                  0
-//#define BLDCFG_1GB_ALIGN                        FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE              UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE              0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT              FALSE
-#define BLDCFG_UMA_ALIGNMENT                    NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
+
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
+
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			TRUE
+
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
+
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_S3_LATE_RESTORE			FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
+
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +39,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 701d7ee19697..7a2cc3b499a6 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -1,160 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
 
-#include <AGESA.h>
-
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT  TRUE
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			TRUE
 
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
-  #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-#define BLDOPT_REMOVE_SRAT            TRUE
-#define BLDOPT_REMOVE_SLIT            TRUE
-#define BLDOPT_REMOVE_WHEA            TRUE
-#define BLDOPT_REMOVE_DMI             TRUE
-#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-#define BLDOPT_REMOVE_ATM_MODE          TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
-//#define BLDOPT_REMOVE_C6_STATE          TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
 
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
 
-#define BLDCFG_VRM_CURRENT_LIMIT                24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT             0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD          24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD       1
-#define BLDCFG_VRM_SLEW_RATE                    5000
-//#define BLDCFG_VRM_NB_SLEW_RATE                 5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY             0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY          0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE            TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE         FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT         6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT      0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0            'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1            '0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB            FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS                3
-//#define BLDCFG_PLATFORM_C1E_MODE                C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA              0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
-#define BLDCFG_PLATFORM_CSTATE_MODE             CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA           0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
-//#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM                  0
-//#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS                0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST         0
-//#define BLDCFG_BUID_SWAP_LIST                   0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST  0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST             0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST              0
-//#define BLDCFG_BUS_NUMBERS_LIST                 0
-//#define BLDCFG_IGNORE_LINK_LIST                 0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST            0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST       0
-//#define BLDCFG_USE_HT_ASSIST                    TRUE
-//#define BLDCFG_USE_ATM_MODE                     TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE       Nfcm
-#define BLDCFG_S3_LATE_RESTORE                    TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH              FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY   FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE       Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD             FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING             FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP       0
-//#define BLDCFG_CFG_GNB_HD_AUDIO                 TRUE
-//#define BLDCFG_CFG_ABM_SUPPORT                  FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE         0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL       0
-//#define BLDCFG_MEM_INIT_PSTATE                  0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE             0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT       DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED             TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE         TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE             QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE            TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE            FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING      FALSE
-#define BLDCFG_MEMORY_POWER_DOWN                TRUE
-#define BLDCFG_POWER_DOWN_MODE                  POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE                     FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE             FALSE
-#define BLDCFG_BANK_SWIZZLE                     TRUE
-#define BLDCFG_TIMING_MODE_SELECT               TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT              DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL             TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM              FALSE
-#define BLDCFG_USE_BURST_MODE                   FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON             FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE               TRUE
-//#define BLDCFG_ECC_REDIRECTION                  FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE                  0
-//#define BLDCFG_SCRUB_L2_RATE                    0
-//#define BLDCFG_SCRUB_L3_RATE                    0
-//#define BLDCFG_SCRUB_IC_RATE                    0
-//#define BLDCFG_SCRUB_DC_RATE                    0
-//#define BLDCFG_ECC_SYNC_FLOOD                   0
-//#define BLDCFG_ECC_SYMBOL_SIZE                  0
-//#define BLDCFG_1GB_ALIGN                        FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE              UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE              0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT              FALSE
-#define BLDCFG_UMA_ALIGNMENT                    NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
+/* Agesa configuration values selection */
+#include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -173,5 +44,5 @@
                   // This string MUST be exactly 12 characters long
 #define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c
index 34561210f7b1..d7558f00917e 100644
--- a/src/mainboard/asrock/imb-a180/buildOpts.c
+++ b/src/mainboard/asrock/imb-a180/buildOpts.c
@@ -1,196 +1,33 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
 
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                  15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+#define BLDOPT_REMOVE_CDIT			TRUE
 
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+/* Build configuration values here. */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			TRUE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -205,54 +42,4 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   imba180_gpio[] = {
-	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
-	{-1}
-};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&imba180_gpio[0])
-
 #include <PlatformInstall.h>
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index d0a8a433ef7f..fe0915b8e503 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -1,16 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <vendorcode/amd/agesa/f16kb/AGESA.h>
 
 /* Include the files that instantiate the configuration definitions. */
@@ -22,251 +11,49 @@
 #include <vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h>
 #include <vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h>
 #include <vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h>
-/* AGESA nonesense: the next three headers depend on heapManager.h */
+/* AGESA nonsense: the next three headers depend on heapManager.h */
 #include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h>
 #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h>
 #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h>
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT3_SOCKET_SUPPORT  TRUE
-
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
-#define BLDOPT_REMOVE_CRAT                     TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 15000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT         21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                 BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS                0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_DESKTOP
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1600_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        FALSE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                TRUE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 FALSE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_1GB_ALIGN                          FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+/* Select the CPU family */
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
+
+/* Select the CPU socket type */
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
+#define BLDOPT_REMOVE_CRAT			TRUE
+#define BLDOPT_REMOVE_CDIT			TRUE
+
+/* Build configuration values here. */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_DESKTOP
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT	DDR1600_FREQUENCY
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
+#define BLDCFG_MEMORY_CLOCK_SELECT		DDR1333_FREQUENCY /* FIXME: Turtle RAM? */
+#define BLDCFG_IGNORE_SPD_CHECKSUM		TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		FALSE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
 
 /*
  * Specify the default values for the VRM controlling the VDDNB plane.
  * If not specified, the values used for the core VRM will be applied
  */
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-
-#if CONFIG(GFXUMA)
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-#endif
-
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO               TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-GPIO_CONTROL   imba180_gpio[] = {
-	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
-	{-1}
-};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&imba180_gpio[0])
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* AGESA nonsense: this header depends on the definitions above */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 65731aae8632..6b57711507ea 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -1,16 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <vendorcode/amd/agesa/f15tn/AGESA.h>
 
 /* Include the files that instantiate the configuration definitions. */
@@ -18,245 +7,55 @@
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
-/* the next two headers depend on heapManager.h */
+/* AGESA nonsense: the next two headers depend on heapManager.h */
 #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
 /* These tables are optional and may be used to adjust memory timing settings */
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_10_SUPPORT FALSE
-#define INSTALL_FAMILY_12_SUPPORT FALSE
-#define INSTALL_FAMILY_14_SUPPORT FALSE
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+/* Select the CPU family */
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
 
-#define INSTALL_FM2_SOCKET_SUPPORT  TRUE
+/* Select the CPU socket type */
+#define INSTALL_FM2_SOCKET_SUPPORT		TRUE
 
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_SODIMMS_SUPPORT          TRUE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 90000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1600_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 FALSE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM        36		// PCIE Spread Spectrum default value 0.36%
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770
-
-#define BLDOPT_REMOVE_ALIB                    FALSE
-#define BLDCFG_PLATFORM_CPB_MODE                  CpbModeDisabled
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
-
-#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         200
-#define BLDCFG_CFG_ABM_SUPPORT                    0
-
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
-
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Trinity
-
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               60000
 
-#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON	3
-#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL	3
+/* Build configuration values here. */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-#if CONFIG(GFXUMA)
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE		  UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE	  	  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */
-#define BLDCFG_UMA_ALLOCATION_SIZE	  	  0x2000//512M
-#define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE
-#endif
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_MEMORY_CLOCK_SELECT		DDR1600_FREQUENCY
+#define BLDCFG_ENABLE_ECC_FEATURE		FALSE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
 
-#define BLDCFG_IOMMU_SUPPORT    TRUE
+#define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
 
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
+#define BLDCFG_IOMMU_SUPPORT			TRUE
 
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+/* Customized OEM build configurations for FCH component */
+#define BLDCFG_FCH_GPP_LINK_CONFIG		PortA1B1C1D1
+#define BLDCFG_FCH_GPP_PORT0_PRESENT		TRUE
+#define BLDCFG_FCH_GPP_PORT1_PRESENT		TRUE
 
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA1B1C1D1
-#define DFLT_FCH_GPP_PORT0_PRESENT          TRUE
-#define DFLT_FCH_GPP_PORT1_PRESENT          TRUE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-//#define FCH_NO_XHCI_SUPPORT			FALSE
-GPIO_CONTROL   f2a85_m_gpio[] = {
-//	{183, Function1, PullUpB},
+GPIO_CONTROL f2a85_m_gpio[] = {
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&f2a85_m_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(f2a85_m_gpio)
 
 /* Moving this include up will break AGESA. */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c
index d4c398adba28..d7558f00917e 100644
--- a/src/mainboard/bap/ode_e20XX/buildOpts.c
+++ b/src/mainboard/bap/ode_e20XX/buildOpts.c
@@ -1,196 +1,33 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
 
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                  15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+#define BLDOPT_REMOVE_CDIT			TRUE
 
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+/* Build configuration values here. */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			TRUE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -205,54 +42,4 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   gizmo2_gpio[] = {
-	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
-	{-1}
-};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&gizmo2_gpio[0])
-
 #include <PlatformInstall.h>
diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c
index f5ac7427278e..d7558f00917e 100644
--- a/src/mainboard/biostar/a68n_5200/buildOpts.c
+++ b/src/mainboard/biostar/a68n_5200/buildOpts.c
@@ -1,196 +1,33 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
 
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                  15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+#define BLDOPT_REMOVE_CDIT			TRUE
 
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+/* Build configuration values here. */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			TRUE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -205,54 +42,4 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   olivehill_gpio[] = {
-	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
-	{-1}
-};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&olivehill_gpio[0])
-
 #include <PlatformInstall.h>
diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c
index 54f92466b378..461561d2e035 100644
--- a/src/mainboard/biostar/am1ml/buildOpts.c
+++ b/src/mainboard/biostar/am1ml/buildOpts.c
@@ -1,196 +1,37 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
 
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                  15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+#define BLDOPT_REMOVE_CDIT			TRUE
 
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+/* Build configuration values here. */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1600_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        FALSE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                TRUE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 FALSE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT	DDR1600_FREQUENCY
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
+#define BLDCFG_MEMORY_CLOCK_SELECT		DDR1333_FREQUENCY /* FIXME: Turtle RAM? */
+#define BLDCFG_IGNORE_SPD_CHECKSUM		TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		FALSE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -205,54 +46,4 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   imba180_gpio[] = {
-	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
-	{-1}
-};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&imba180_gpio[0])
-
 #include <PlatformInstall.h>
diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c
index be07053185b2..d8d46d499e6f 100644
--- a/src/mainboard/elmex/pcm205400/buildOpts.c
+++ b/src/mainboard/elmex/pcm205400/buildOpts.c
@@ -1,160 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
 
-/* Select the cpu socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
 
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						FALSE
-#define BLDOPT_REMOVE_SLIT						FALSE
-#define BLDOPT_REMOVE_WHEA						FALSE
-#define BLDOPT_REMOVE_DMI						TRUE
-#define BLDOPT_REMOVE_HT_ASSIST					TRUE
-#define BLDOPT_REMOVE_ATM_MODE					TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_C6_STATE				TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
 
-#define BLDCFG_VRM_CURRENT_LIMIT				24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
-#define BLDCFG_VRM_SLEW_RATE					5000
-//#define BLDCFG_VRM_NB_SLEW_RATE				5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS				3
-//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA			0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
-#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM				0
-//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
-//#define BLDCFG_BUID_SWAP_LIST					0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
-//#define BLDCFG_BUS_NUMBERS_LIST				0
-//#define BLDCFG_IGNORE_LINK_LIST				0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
-//#define BLDCFG_USE_HT_ASSIST					TRUE
-//#define BLDCFG_USE_ATM_MODE					TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
-#define BLDCFG_S3_LATE_RESTORE					TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
-#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
-//#define BLDCFG_MEM_INIT_PSTATE				0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
-#define BLDCFG_MEMORY_POWER_DOWN				TRUE
-#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE					FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
-#define BLDCFG_BANK_SWIZZLE						TRUE
-#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
-#define BLDCFG_USE_BURST_MODE					FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
-//#define BLDCFG_ECC_REDIRECTION				FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE				0
-//#define BLDCFG_SCRUB_L2_RATE					0
-//#define BLDCFG_SCRUB_L3_RATE					0
-//#define BLDCFG_SCRUB_IC_RATE					0
-//#define BLDCFG_SCRUB_DC_RATE					0
-//#define BLDCFG_ECC_SYNC_FLOOD					0
-//#define BLDCFG_ECC_SYMBOL_SIZE				0
-//#define BLDCFG_1GB_ALIGN						FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE				UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE				0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
-#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +38,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index 91c2182361d3..d8d46d499e6f 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -1,160 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
 
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
 
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						FALSE
-#define BLDOPT_REMOVE_SLIT						FALSE
-#define BLDOPT_REMOVE_WHEA						FALSE
-#define BLDOPT_REMOVE_DMI						TRUE
-#define BLDOPT_REMOVE_HT_ASSIST					TRUE
-#define BLDOPT_REMOVE_ATM_MODE					TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_C6_STATE				TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
 
-#define BLDCFG_VRM_CURRENT_LIMIT				24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
-#define BLDCFG_VRM_SLEW_RATE					5000
-//#define BLDCFG_VRM_NB_SLEW_RATE				5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS				3
-//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA			0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
-#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM				0
-//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
-//#define BLDCFG_BUID_SWAP_LIST					0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
-//#define BLDCFG_BUS_NUMBERS_LIST				0
-//#define BLDCFG_IGNORE_LINK_LIST				0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
-//#define BLDCFG_USE_HT_ASSIST					TRUE
-//#define BLDCFG_USE_ATM_MODE					TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
-#define BLDCFG_S3_LATE_RESTORE					TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
-#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
-//#define BLDCFG_MEM_INIT_PSTATE				0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
-#define BLDCFG_MEMORY_POWER_DOWN				TRUE
-#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE					FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
-#define BLDCFG_BANK_SWIZZLE						TRUE
-#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
-#define BLDCFG_USE_BURST_MODE					FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
-//#define BLDCFG_ECC_REDIRECTION				FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE				0
-//#define BLDCFG_SCRUB_L2_RATE					0
-//#define BLDCFG_SCRUB_L3_RATE					0
-//#define BLDCFG_SCRUB_IC_RATE					0
-//#define BLDCFG_SCRUB_DC_RATE					0
-//#define BLDCFG_ECC_SYNC_FLOOD					0
-//#define BLDCFG_ECC_SYMBOL_SIZE				0
-//#define BLDCFG_1GB_ALIGN						FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE				UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE				0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
-#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +38,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
index d4c398adba28..d7558f00917e 100644
--- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
@@ -1,196 +1,33 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <AGESA.h>
 
-#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
 
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                  15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+#define BLDOPT_REMOVE_CDIT			TRUE
 
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+/* Build configuration values here. */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			TRUE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -205,54 +42,4 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   gizmo2_gpio[] = {
-	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
-	{-1}
-};
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&gizmo2_gpio[0])
-
 #include <PlatformInstall.h>
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
index 12974844ec82..2d1128644b0b 100644
--- a/src/mainboard/hp/abm/buildOpts.c
+++ b/src/mainboard/hp/abm/buildOpts.c
@@ -1,201 +1,34 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 23714 $   @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
- */
-
 #include <AGESA.h>
 
-#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
-
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
-
-#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
-  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
-    #undef INSTALL_FT3_SOCKET_SUPPORT
-    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
-  #endif
-#endif
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
-#define BLDOPT_REMOVE_CRAT                     TRUE
-#define BLDOPT_REMOVE_CDIT                     TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
+#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
 
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                  15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
-#define BLDCFG_VRM_SLEW_RATE                      10000
-#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
+#define BLDOPT_REMOVE_CRAT			TRUE
+#define BLDOPT_REMOVE_CDIT			TRUE
 
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
-                                                         // core for C-state entry requests. A value
-                                                         // of 0 in this field specifies that the core
-                                                         // does not trap any IO addresses for C-state entry.
-                                                         // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+/* Build configuration values here. */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
 
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE                UMA_NONE
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT                      FALSE
-#define OPTION_GFX_INIT_SVIEW                     FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			TRUE
+#define BLDCFG_UMA_ALLOCATION_MODE		UMA_NONE
+#define BLDCFG_IOMMU_SUPPORT			FALSE
 
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
-#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-#ifdef PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
-#endif
-
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /* Include the files that instantiate the configuration definitions. */
 #include "cpuRegisters.h"
@@ -210,51 +43,7 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-GPIO_CONTROL   hp_abm_gpio[] = {
+GPIO_CONTROL hp_abm_gpio[] = {
 	{ 45, Function2, GpioOutEnB | Sticky },                   // Signal input  APU_SD_LED
 	{ 49, Function2, PullUpB | PullDown | Sticky },           // Signal output APU_ABM_LED_UID
 	{ 50, Function2, PullUpB | PullDown | Sticky },           // Signal output APU_ABM_LED_HEALTH
@@ -267,6 +56,6 @@ GPIO_CONTROL   hp_abm_gpio[] = {
 	{ 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&hp_abm_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(hp_abm_gpio)
 
 #include <PlatformInstall.h>
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 107c9937dc21..3aad89c15ef3 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -1,16 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include "mainboard.h"
 
 #include <vendorcode/amd/agesa/f15tn/AGESA.h>
@@ -20,237 +9,44 @@
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
-/* AGESA nonesense: the next two headers depend on heapManager.h */
+/* AGESA nonsense: the next two headers depend on heapManager.h */
 #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
 /* These tables are optional and may be used to adjust memory timing settings */
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_10_SUPPORT FALSE
-#define INSTALL_FAMILY_12_SUPPORT FALSE
-#define INSTALL_FAMILY_14_SUPPORT FALSE
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  TRUE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  TRUE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+/* Select the CPU family */
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
 
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+/* Select the CPU socket type */
+#define INSTALL_FS1_SOCKET_SUPPORT		TRUE
+#define INSTALL_FP2_SOCKET_SUPPORT		TRUE
 
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 90000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM        36		// PCIE Spread Spectrum default value 0.36%
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770
-
-#define BLDOPT_REMOVE_ALIB                    FALSE
-#define BLDCFG_PLATFORM_CPB_MODE                  CpbModeDisabled
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
-
-#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         200
-#define BLDCFG_CFG_ABM_SUPPORT                    0
 
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+/* Build configuration values here. */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Trinity
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
 
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               60000
+#define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
 
-#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON	3
-#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL	3
+#define BLDCFG_IOMMU_SUPPORT			TRUE
 
-#if CONFIG(GFXUMA)
-#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE		  UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE		  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */
-#define BLDCFG_UMA_ALLOCATION_SIZE		  0x2000//512M
-#define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE
-#endif
-
-#define BLDCFG_IOMMU_SUPPORT    TRUE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /*
  * The GPIO control is not well documented in AGESA, but is in the BKDG
@@ -279,9 +75,10 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = {
 	{57, Function1, OUTPUT_HIGH | PULL_NONE},	/* WLAN enable */
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&pavilion_m6_1035dx_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(pavilion_m6_1035dx_gpio)
 
-/* These definitions could be moved to a common Hudson header, should we decide
+/*
+ * These definitions could be moved to a common Hudson header, should we decide
  * to provide our own, saner SCI mapping function
  */
 #define GEVENT_PIN(gpe)		((gpe) + 0x40)
@@ -299,7 +96,11 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
 	{SCI_MAP_XHCI_10_0, PME_GPE},
 	{SCI_MAP_PWRBTN, PME_GPE},
 };
-#define BLDCFG_FCH_SCI_MAP_LIST			(&m6_1035dx_sci_map[0])
+#define BLDCFG_FCH_SCI_MAP_LIST			(m6_1035dx_sci_map)
 
-/* AGESA nonsense: this header depends on the definitions above */
+/*
+ * Process the options...
+ * This file include MUST occur AFTER the user option selection settings.
+ * AGESA nonsense: Moving this include up will break AGESA.
+ */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 3bc97ea97a8b..d8d46d499e6f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -1,165 +1,42 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
-#include <vendorcode/amd/agesa/f14/AGESA.h>
-
-/* Include the files that instantiate the configuration definitions. */
-#include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
-/* AGESA nonesense: the next two headers depend on heapManager.h */
-#include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h>
-/* These tables are optional and may be used to adjust memory timing settings */
-#include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h>
-#include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h>
-
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
-
-/**
- * AGESA optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-		#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-		#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-		#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-		#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-		#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-		#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-		#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						FALSE
-#define BLDOPT_REMOVE_SLIT						FALSE
-#define BLDOPT_REMOVE_WHEA						FALSE
-#define BLDOPT_REMOVE_DMI						TRUE
-#define BLDOPT_REMOVE_HT_ASSIST					TRUE
-#define BLDOPT_REMOVE_ATM_MODE					TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_C6_STATE				TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
-
-#define BLDCFG_VRM_CURRENT_LIMIT				24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
-#define BLDCFG_VRM_SLEW_RATE					5000
-//#define BLDCFG_VRM_NB_SLEW_RATE				5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS				3
-//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA			0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
-#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM				0
-//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
-//#define BLDCFG_BUID_SWAP_LIST					0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
-//#define BLDCFG_BUS_NUMBERS_LIST				0
-//#define BLDCFG_IGNORE_LINK_LIST				0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
-//#define BLDCFG_USE_HT_ASSIST					TRUE
-//#define BLDCFG_USE_ATM_MODE					TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
-#define BLDCFG_S3_LATE_RESTORE					TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
-#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
-//#define BLDCFG_MEM_INIT_PSTATE				0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
-#define BLDCFG_MEMORY_POWER_DOWN				TRUE
-#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE					FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
-#define BLDCFG_BANK_SWIZZLE						TRUE
-#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
-#define BLDCFG_USE_BURST_MODE					FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
-//#define BLDCFG_ECC_REDIRECTION				FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE				0
-//#define BLDCFG_SCRUB_L2_RATE					0
-//#define BLDCFG_SCRUB_L3_RATE					0
-//#define BLDCFG_SCRUB_IC_RATE					0
-//#define BLDCFG_SCRUB_DC_RATE					0
-//#define BLDCFG_ECC_SYNC_FLOOD					0
-//#define BLDCFG_ECC_SYMBOL_SIZE				0
-//#define BLDCFG_1GB_ALIGN						FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE				UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE				0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
-#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
-
-/* AGESA nonsense: this header depends on the definitions above */
-/* Instantiate all solution relevant data. */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
+
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
+
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
+
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
+
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
+
+/* Agesa configuration values selection */
+#include <AGESA.h>
+
+/* Include the files that instantiate the configuration definitions */
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index c78c5c5374e2..c0a87ddb21e9 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -1,16 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include "mainboard.h"
 
 #include <vendorcode/amd/agesa/f15tn/AGESA.h>
@@ -20,237 +9,44 @@
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
-/* AGESA nonesense: the next two headers depend on heapManager.h */
+/* AGESA nonsense: the next two headers depend on heapManager.h */
 #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
 /* These tables are optional and may be used to adjust memory timing settings */
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_10_SUPPORT FALSE
-#define INSTALL_FAMILY_12_SUPPORT FALSE
-#define INSTALL_FAMILY_14_SUPPORT FALSE
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  TRUE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  TRUE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+/* Select the CPU family */
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
 
-#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+/* Select the CPU socket type */
+#define INSTALL_FS1_SOCKET_SUPPORT		TRUE
+#define INSTALL_FP2_SOCKET_SUPPORT		TRUE
 
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 90000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM        36		// PCIE Spread Spectrum default value 0.36%
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770
-
-#define BLDOPT_REMOVE_ALIB                    FALSE
-#define BLDCFG_PLATFORM_CPB_MODE                  CpbModeDisabled
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
-
-#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         200
-#define BLDCFG_CFG_ABM_SUPPORT                    0
 
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+/* Build configuration values here */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Trinity
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
 
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               60000
-
-#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON	3
-#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL	3
-
-#if CONFIG(GFXUMA)
-#define BLDCFG_UMA_ALIGNMENT			UMA_4MB_ALIGNED
 #define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE		0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */
-#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000//512M
-#define BLDCFG_UMA_ABOVE4G_SUPPORT		FALSE
-#endif
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
 
-#define BLDCFG_IOMMU_SUPPORT    TRUE
+#define BLDCFG_IOMMU_SUPPORT			TRUE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
-
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
-
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
 /*
  * The GPIO control is not well documented in AGESA, but is in the BKDG
@@ -279,9 +75,10 @@ GPIO_CONTROL lenovo_g505s_gpio[] = {
 	{57, Function1, OUTPUT_HIGH | PULL_NONE},	/* WLAN enable */
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&lenovo_g505s_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(lenovo_g505s_gpio)
 
-/* These definitions could be moved to a common Hudson header, should we decide
+/*
+ * These definitions could be moved to a common Hudson header, should we decide
  * to provide our own, saner SCI mapping function
  */
 #define GEVENT_PIN(gpe)		((gpe) + 0x40)
@@ -299,7 +96,11 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
 	{SCI_MAP_XHCI_10_0, PME_GPE},
 	{SCI_MAP_PWRBTN, PME_GPE},
 };
-#define BLDCFG_FCH_SCI_MAP_LIST			(&lenovo_g505s_sci_map[0])
+#define BLDCFG_FCH_SCI_MAP_LIST			(lenovo_g505s_sci_map)
 
-/* AGESA nonsense: this header depends on the definitions above */
+/*
+ * Process the options...
+ * This file include MUST occur AFTER the user option selection settings.
+ * AGESA nonsense: Moving this include up will break AGESA.
+ */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 91c2182361d3..d8d46d499e6f 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -1,160 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
 
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
 
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						FALSE
-#define BLDOPT_REMOVE_SLIT						FALSE
-#define BLDOPT_REMOVE_WHEA						FALSE
-#define BLDOPT_REMOVE_DMI						TRUE
-#define BLDOPT_REMOVE_HT_ASSIST					TRUE
-#define BLDOPT_REMOVE_ATM_MODE					TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_C6_STATE				TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
 
-#define BLDCFG_VRM_CURRENT_LIMIT				24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
-#define BLDCFG_VRM_SLEW_RATE					5000
-//#define BLDCFG_VRM_NB_SLEW_RATE				5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS				3
-//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA			0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
-#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM				0
-//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
-//#define BLDCFG_BUID_SWAP_LIST					0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
-//#define BLDCFG_BUS_NUMBERS_LIST				0
-//#define BLDCFG_IGNORE_LINK_LIST				0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
-//#define BLDCFG_USE_HT_ASSIST					TRUE
-//#define BLDCFG_USE_ATM_MODE					TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
-#define BLDCFG_S3_LATE_RESTORE					TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
-#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
-//#define BLDCFG_MEM_INIT_PSTATE				0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
-#define BLDCFG_MEMORY_POWER_DOWN				TRUE
-#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE					FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
-#define BLDCFG_BANK_SWIZZLE						TRUE
-#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
-#define BLDCFG_USE_BURST_MODE					FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
-//#define BLDCFG_ECC_REDIRECTION				FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE				0
-//#define BLDCFG_SCRUB_L2_RATE					0
-//#define BLDCFG_SCRUB_L3_RATE					0
-//#define BLDCFG_SCRUB_IC_RATE					0
-//#define BLDCFG_SCRUB_DC_RATE					0
-//#define BLDCFG_ECC_SYNC_FLOOD					0
-//#define BLDCFG_ECC_SYMBOL_SIZE				0
-//#define BLDCFG_1GB_ALIGN						FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE				UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE				0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
-#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +38,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 91c2182361d3..d8d46d499e6f 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -1,160 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
 
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
 
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						FALSE
-#define BLDOPT_REMOVE_SLIT						FALSE
-#define BLDOPT_REMOVE_WHEA						FALSE
-#define BLDOPT_REMOVE_DMI						TRUE
-#define BLDOPT_REMOVE_HT_ASSIST					TRUE
-#define BLDOPT_REMOVE_ATM_MODE					TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_C6_STATE				TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
 
-#define BLDCFG_VRM_CURRENT_LIMIT				24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
-#define BLDCFG_VRM_SLEW_RATE					5000
-//#define BLDCFG_VRM_NB_SLEW_RATE				5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS				3
-//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA			0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
-#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM				0
-//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
-//#define BLDCFG_BUID_SWAP_LIST					0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
-//#define BLDCFG_BUS_NUMBERS_LIST				0
-//#define BLDCFG_IGNORE_LINK_LIST				0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
-//#define BLDCFG_USE_HT_ASSIST					TRUE
-//#define BLDCFG_USE_ATM_MODE					TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
-#define BLDCFG_S3_LATE_RESTORE					TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
-#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
-//#define BLDCFG_MEM_INIT_PSTATE				0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
-#define BLDCFG_MEMORY_POWER_DOWN				TRUE
-#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE					FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
-#define BLDCFG_BANK_SWIZZLE						TRUE
-#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
-#define BLDCFG_USE_BURST_MODE					FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
-//#define BLDCFG_ECC_REDIRECTION				FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE				0
-//#define BLDCFG_SCRUB_L2_RATE					0
-//#define BLDCFG_SCRUB_L3_RATE					0
-//#define BLDCFG_SCRUB_IC_RATE					0
-//#define BLDCFG_SCRUB_DC_RATE					0
-//#define BLDCFG_ECC_SYNC_FLOOD					0
-//#define BLDCFG_ECC_SYMBOL_SIZE				0
-//#define BLDCFG_1GB_ALIGN						FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE				UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE				0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
-#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +38,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c
index 61858940c050..5740382985ce 100644
--- a/src/mainboard/msi/ms7721/buildOpts.c
+++ b/src/mainboard/msi/ms7721/buildOpts.c
@@ -1,16 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
 #include <vendorcode/amd/agesa/f15tn/AGESA.h>
 
 /* Include the files that instantiate the configuration definitions. */
@@ -18,245 +7,60 @@
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
-/* the next two headers depend on heapManager.h */
+/* AGESA nonsense: the next two headers depend on heapManager.h */
 #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
 /* These tables are optional and may be used to adjust memory timing settings */
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
 
-/* Select the CPU family. */
-#define INSTALL_FAMILY_10_SUPPORT FALSE
-#define INSTALL_FAMILY_12_SUPPORT FALSE
-#define INSTALL_FAMILY_14_SUPPORT FALSE
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+/* Select the CPU family */
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
 
-#define INSTALL_FM2_SOCKET_SUPPORT  TRUE
+/* Select the CPU socket type */
+#define INSTALL_FM2_SOCKET_SUPPORT		TRUE
 
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_SODIMMS_SUPPORT          TRUE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
-#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
-#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
 #define	BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 90000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1600_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 FALSE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_DRAM_RATE                    0
-#define BLDCFG_SCRUB_L2_RATE                      0
-#define BLDCFG_SCRUB_L3_RATE                      0
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_SCRUB_DC_RATE                      0
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM        36		// PCIE Spread Spectrum default value 0.36%
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770
-
-#define BLDOPT_REMOVE_ALIB                    FALSE
-#define BLDCFG_PLATFORM_CPB_MODE                  CpbModeDisabled
-#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
-
-#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         200
-#define BLDCFG_CFG_ABM_SUPPORT                    0
 
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+/* Build configuration values here */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
 
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Trinity
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_MEMORY_CLOCK_SELECT		DDR1600_FREQUENCY
+#define BLDCFG_ENABLE_ECC_FEATURE		FALSE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
 
-#define BLDCFG_VRM_NB_CURRENT_LIMIT               60000
-
-#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON	3
-#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL	3
-
-#if CONFIG(GFXUMA)
-#define BLDCFG_UMA_ALIGNMENT			UMA_4MB_ALIGNED
 #define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE		0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */
-#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000//512M
-#define BLDCFG_UMA_ABOVE4G_SUPPORT		FALSE
-#endif
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
 
-#define BLDCFG_IOMMU_SUPPORT    TRUE
+#define BLDCFG_IOMMU_SUPPORT			TRUE
 
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
 
-/* Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-/*
- * Customized OEM build configurations for FCH component
- */
-// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
-// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
-// #define BLDCFG_AZALIA_SSID                    0x780D1022
-// #define BLDCFG_SMBUS_SSID                     0x780B1022
-// #define BLDCFG_IDE_SSID                       0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
-// #define BLDCFG_SATA_IDE_SSID                  0x78001022
-// #define BLDCFG_SATA_RAID5_SSID                0x78031022
-// #define BLDCFG_SATA_RAID_SSID                 0x78021022
-// #define BLDCFG_EHCI_SSID                      0x78081022
-// #define BLDCFG_OHCI_SSID                      0x78071022
-// #define BLDCFG_LPC_SSID                       0x780E1022
-// #define BLDCFG_SD_SSID                        0x78061022
-// #define BLDCFG_XHCI_SSID                      0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+/* Customized OEM build configurations for FCH component */
+#define BLDCFG_FCH_GPP_LINK_CONFIG		PortA1B1C1D1
+#define BLDCFG_FCH_GPP_PORT0_PRESENT		TRUE
+#define BLDCFG_FCH_GPP_PORT1_PRESENT		TRUE
 
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
-/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
-#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
-#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
-#define DFLT_HPET_BASE_ADDRESS              0xFED00000
-#define DFLT_SMI_CMD_PORT                   0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
-#define DFLT_GEC_BASE_ADDRESS               0xFED61000
-#define DFLT_AZALIA_SSID                    0x780D1022
-#define DFLT_SMBUS_SSID                     0x780B1022
-#define DFLT_IDE_SSID                       0x780C1022
-#define DFLT_SATA_AHCI_SSID                 0x78011022
-#define DFLT_SATA_IDE_SSID                  0x78001022
-#define DFLT_SATA_RAID5_SSID                0x78031022
-#define DFLT_SATA_RAID_SSID                 0x78021022
-#define DFLT_EHCI_SSID                      0x78081022
-#define DFLT_OHCI_SSID                      0x78071022
-#define DFLT_LPC_SSID                       0x780E1022
-#define DFLT_SD_SSID                        0x78061022
-#define DFLT_XHCI_SSID                      0x78121022
-#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
-#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
-#define DFLT_FCH_GPP_LINK_CONFIG            PortA1B1C1D1
-#define DFLT_FCH_GPP_PORT0_PRESENT          TRUE
-#define DFLT_FCH_GPP_PORT1_PRESENT          TRUE
-#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
-//#define FCH_NO_XHCI_SUPPORT			FALSE
-GPIO_CONTROL   ms7721_m_gpio[] = {
-//	{183, Function1, PullUpB},
+GPIO_CONTROL ms7721_m_gpio[] = {
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&ms7721_m_gpio[0])
 
-/* Moving this include up will break AGESA. */
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(ms7721_m_gpio)
+
+/*
+ * Process the options...
+ * This file include MUST occur AFTER the user option selection settings.
+ * AGESA nonsense: Moving this include up will break AGESA.
+ */
 #include <PlatformInstall.h>
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index 3a14ce5a2591..255893833cf6 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -1,160 +1,33 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/**
- * @file
- *
- * AMD User options selection for a Brazos platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- * For Information about this file, see @ref platforminstall.
- */
-
-/* Select the CPU family. */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-/* Select the CPU socket type. */
-#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
-
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						FALSE
-#define BLDOPT_REMOVE_SLIT						FALSE
-#define BLDOPT_REMOVE_WHEA						FALSE
-#define BLDOPT_REMOVE_DMI						FALSE
-#define BLDOPT_REMOVE_HT_ASSIST					TRUE
-#define BLDOPT_REMOVE_ATM_MODE					TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
-//#define BLDOPT_REMOVE_C6_STATE				TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
-
-#define BLDCFG_VRM_CURRENT_LIMIT				24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
-#define BLDCFG_VRM_SLEW_RATE					5000
-//#define BLDCFG_VRM_NB_SLEW_RATE				5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS				3
-//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA			0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
-#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
-//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
-#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM				0
-//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
-//#define BLDCFG_BUID_SWAP_LIST					0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
-//#define BLDCFG_BUS_NUMBERS_LIST				0
-//#define BLDCFG_IGNORE_LINK_LIST				0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
-//#define BLDCFG_USE_HT_ASSIST					TRUE
-//#define BLDCFG_USE_ATM_MODE					TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
-#define BLDCFG_S3_LATE_RESTORE					TRUE
-//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
-#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
-//#define BLDCFG_MEM_INIT_PSTATE				0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
-#define BLDCFG_MEMORY_POWER_DOWN				TRUE
-#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE					FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
-#define BLDCFG_BANK_SWIZZLE						TRUE
-#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
-#define BLDCFG_USE_BURST_MODE					FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
-//#define BLDCFG_ECC_REDIRECTION				FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE				0
-//#define BLDCFG_SCRUB_L2_RATE					0
-//#define BLDCFG_SCRUB_L3_RATE					0
-//#define BLDCFG_SCRUB_IC_RATE					0
-//#define BLDCFG_SCRUB_DC_RATE					0
-//#define BLDCFG_ECC_SYNC_FLOOD					0
-//#define BLDCFG_ECC_SYMBOL_SIZE				0
-//#define BLDCFG_1GB_ALIGN						FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE				UMA_NONE
-#define BLDCFG_UMA_ALLOCATION_SIZE				0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
-#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
+/* Select the CPU family */
+#define INSTALL_FAMILY_14_SUPPORT		TRUE
+
+/* Select the CPU socket type */
+#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
+
+/* Agesa optional capabilities selection */
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
+#define BLDOPT_ENABLE_DMI			TRUE
+
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
+
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
+#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
+#define BLDCFG_UMA_ALLOCATION_MODE		UMA_NONE
+
+/* Agesa configuration values selection */
 #include <AGESA.h>
 
-/* Include the files that instantiate the configuration definitions. */
-
+/* Include the files that instantiate the configuration definitions */
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -167,5 +40,5 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-// Instantiate all solution relevant data.
+/* Instantiate all solution relevant data */
 #include <PlatformInstall.h>
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 883d509bca38..31472b2c2eb2 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -206,8 +206,6 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
     #define OPTION_SW_DRAM_INIT  TRUE
     #undef OPTION_S3_MEM_SUPPORT
     #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY  TRUE
     #undef OPTION_C6_STATE
     #define OPTION_C6_STATE  TRUE
     #undef OPTION_CPB
@@ -238,7 +236,7 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 #define OPTION_ACPI_PSTATES             TRUE
 #define OPTION_WHEA                     TRUE
-#define OPTION_DMI                      TRUE
+#define OPTION_DMI                      FALSE
 #define OPTION_EARLY_SAMPLES            FALSE
 #define CFG_ACPI_PSTATES_PPC            TRUE
 #define CFG_ACPI_PSTATES_PCT            TRUE
@@ -246,7 +244,7 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 #define CFG_ACPI_PSTATES_PSS            TRUE
 #define CFG_ACPI_PSTATES_XPSS           TRUE
 #define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
 #define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
 #define OPTION_ALIB                     TRUE
 /*---------------------------------------------------------------------------
@@ -312,10 +310,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
     #define OPTION_PARALLEL_TRAINING    FALSE
   #endif
 #endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
-  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
     #undef  OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE         FALSE
+    #define OPTION_ONLINE_SPARE         TRUE
   #endif
 #endif
 #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
@@ -348,10 +347,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
     #define OPTION_WHEA                 FALSE
   #endif
 #endif
-#ifdef BLDOPT_REMOVE_DMI
-  #if  BLDOPT_REMOVE_DMI == TRUE
+/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_DMI
+  #if  BLDOPT_ENABLE_DMI == TRUE
     #undef  OPTION_DMI
-    #define OPTION_DMI                  FALSE
+    #define OPTION_DMI                  TRUE
   #endif
 #endif
 #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
@@ -389,10 +389,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
   #endif
 #endif
 
-#ifdef BLDOPT_REMOVE_GFX_RECOVERY
-  #if  BLDOPT_REMOVE_GFX_RECOVERY == TRUE
+/* Originally BLDOPT_REMOVE_GFX_RECOVERY, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_GFX_RECOVERY
+  #if  BLDOPT_ENABLE_GFX_RECOVERY == TRUE
     #undef  OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY         FALSE
+    #define OPTION_GFX_RECOVERY         TRUE
   #endif
 #endif
 
@@ -438,10 +439,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
   #endif
 #endif
 
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
-  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
+#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
     #undef  CFG_VRM_HIGH_SPEED_ENABLE
-    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
   #endif
 #endif
 
@@ -571,13 +573,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_VRM_CURRENT_LIMIT
   #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
 #else
-  #define CFG_VRM_CURRENT_LIMIT            0
+  #define CFG_VRM_CURRENT_LIMIT            24000
 #endif
 
 #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
   #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
 #else
-  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+  #define CFG_VRM_LOW_POWER_THRESHOLD      24000
 #endif
 
 #ifdef BLDCFG_VRM_SLEW_RATE
@@ -589,7 +591,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
   #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
 #else
-  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     (6000)
 #endif
 
 #ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
@@ -626,7 +628,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_PLAT_NUM_IO_APICS
   #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
 #else
-  #define CFG_PLAT_NUM_IO_APICS            0
+  #define CFG_PLAT_NUM_IO_APICS            3
 #endif
 
 #ifdef BLDCFG_MEM_INIT_PSTATE
@@ -662,19 +664,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_PLATFORM_CSTATE_MODE
   #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
 #else
-  #define CFG_CSTATE_MODE                     CStateModeDisabled
+  #define CFG_CSTATE_MODE                     CStateModeC6
 #endif
 
 #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
   #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
 #else
-  #define CFG_CSTATE_OPDATA                   0
+  #define CFG_CSTATE_OPDATA                   0x840
 #endif
 
 #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
   #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
 #else
-  #define CFG_CSTATE_IO_BASE_ADDRESS       0
+  #define CFG_CSTATE_IO_BASE_ADDRESS       0x840
 #endif
 
 #ifdef BLDCFG_PLATFORM_CPB_MODE
@@ -686,7 +688,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_CORE_LEVELING_MODE
   #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
 #else
-  #define CFG_CORE_LEVELING_MODE           0
+  #define CFG_CORE_LEVELING_MODE           CORE_LEVEL_LOWEST
 #endif
 
 #ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
@@ -704,7 +706,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
   #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
 #else
-  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR1333_FREQUENCY
 #endif
 
 #ifdef BLDCFG_MEMORY_MODE_UNGANGED
@@ -770,13 +772,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_POWER_DOWN
   #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
 #else
-  #define CFG_MEMORY_POWER_DOWN                 FALSE
+  #define CFG_MEMORY_POWER_DOWN                 TRUE
 #endif
 
 #ifdef BLDCFG_POWER_DOWN_MODE
   #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
 #else
-  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_MODE_AUTO
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHIP_SELECT
 #endif
 
 #ifdef BLDCFG_ONLINE_SPARE
@@ -806,7 +808,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_CLOCK_SELECT
   #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
 #else
-  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+  #define CFG_MEMORY_CLOCK_SELECT               DDR1333_FREQUENCY
 #endif
 
 #ifdef BLDCFG_DQS_TRAINING_CONTROL
@@ -878,7 +880,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_ECC_SYNC_FLOOD
   #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
 #else
-  #define CFG_ECC_SYNC_FLOOD          0
+  #define CFG_ECC_SYNC_FLOOD          FALSE
 #endif
 
 #ifdef BLDCFG_ECC_SYMBOL_SIZE
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
index 4a8237a210fc..5ea5fd15950b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
@@ -48,6 +48,47 @@
   #define  FCH_SUPPORT   FALSE
 #endif
 
+/* Define the default values for the FCH configuration settings */
+#define DFLT_SMBUS0_BASE_ADDRESS		0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS		0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS		0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS		0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS		0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS		0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS		0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS		0x820
+#define DFLT_SPI_BASE_ADDRESS			0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS	0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS			0xFED00000
+#define DFLT_SMI_CMD_PORT			0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS		0xFE00
+#define DFLT_GEC_BASE_ADDRESS			0xFED61000
+#define DFLT_AZALIA_SSID			0x780D1022
+#define DFLT_SMBUS_SSID				0x780B1022
+#define DFLT_IDE_SSID				0x780C1022
+#define DFLT_SATA_AHCI_SSID			0x78011022
+#define DFLT_SATA_IDE_SSID			0x78001022
+#define DFLT_SATA_RAID5_SSID			0x78031022
+#define DFLT_SATA_RAID_SSID			0x78021022
+#define DFLT_EHCI_SSID				0x78081022
+#define DFLT_OHCI_SSID				0x78071022
+#define DFLT_LPC_SSID				0x780E1022
+#define DFLT_SD_SSID				0x78061022
+#define DFLT_XHCI_SSID				0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB		FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP		TRUE
+
+#define DFLT_FCH_GPP_LINK_CONFIG		PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT		FALSE
+
+#define DFLT_FCH_GPP_PORT0_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG		FALSE
 
 /* ACPI block register offset definitions */
 #define PM1_STATUS_OFFSET              0x00
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
index 1bca38800046..8bdbb92165b6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
@@ -424,6 +424,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 #define OPTION_NODE_INTERLEAVE                  FALSE
 #define OPTION_PARALLEL_TRAINING                FALSE
 #define OPTION_ONLINE_SPARE                     FALSE
+#define OPTION_ONLINE_SPARE_CAPABLE             FALSE
 #define OPTION_MEM_RESTORE                      FALSE
 #define OPTION_DIMM_EXCLUDE                     FALSE
 
@@ -503,8 +504,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_PARALLEL_TRAINING  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -579,8 +580,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_NODE_INTERLEAVE  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -640,8 +641,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_PARALLEL_TRAINING  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -718,8 +719,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_NODE_INTERLEAVE  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -767,8 +768,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_PARALLEL_TRAINING  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -1123,8 +1124,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_DCT_INTERLEAVE  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -1301,8 +1302,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_PARALLEL_TRAINING  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -1367,8 +1368,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_NODE_INTERLEAVE  TRUE
     #undef OPTION_MEM_RESTORE
     #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_ONLINE_SPARE_CAPABLE
+    #define OPTION_ONLINE_SPARE_CAPABLE TRUE
     #undef OPTION_DIMM_EXCLUDE
     #define OPTION_DIMM_EXCLUDE  TRUE
   #endif
@@ -1384,7 +1385,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 
 #define OPTION_ACPI_PSTATES             TRUE
 #define OPTION_WHEA                     TRUE
-#define OPTION_DMI                      TRUE
+#define OPTION_DMI                      FALSE
 #define OPTION_EARLY_SAMPLES            FALSE
 #define CFG_ACPI_PSTATES_PPC            TRUE
 #define CFG_ACPI_PSTATES_PCT            TRUE
@@ -1392,7 +1393,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 #define CFG_ACPI_PSTATES_PSS            TRUE
 #define CFG_ACPI_PSTATES_XPSS           TRUE
 #define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
 #define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
 #define OPTION_ALIB                     TRUE
 /*---------------------------------------------------------------------------
@@ -1464,10 +1465,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_PARALLEL_TRAINING    FALSE
   #endif
 #endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
-  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
     #undef  OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE         FALSE
+    #define OPTION_ONLINE_SPARE         OPTION_ONLINE_SPARE_CAPABLE
   #endif
 #endif
 #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
@@ -1506,10 +1508,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
     #define OPTION_WHEA                 FALSE
   #endif
 #endif
-#ifdef BLDOPT_REMOVE_DMI
-  #if  BLDOPT_REMOVE_DMI == TRUE
+/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_DMI
+  #if  BLDOPT_ENABLE_DMI == TRUE
     #undef  OPTION_DMI
-    #define OPTION_DMI                  FALSE
+    #define OPTION_DMI                  TRUE
   #endif
 #endif
 #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
@@ -1611,10 +1614,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
   #endif
 #endif
 
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
-  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
+#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
     #undef  CFG_VRM_HIGH_SPEED_ENABLE
-    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
   #endif
 #endif
 
@@ -1762,7 +1766,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_VRM_CURRENT_LIMIT
   #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
 #else
-  #define CFG_VRM_CURRENT_LIMIT            0
+  #define CFG_VRM_CURRENT_LIMIT            90000
 #endif
 
 #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
@@ -1824,7 +1828,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
   #define CFG_VRM_NB_CURRENT_LIMIT         BLDCFG_VRM_NB_CURRENT_LIMIT
 #else
-  #define CFG_VRM_NB_CURRENT_LIMIT         (0)
+  #define CFG_VRM_NB_CURRENT_LIMIT         (60000)
 #endif
 
 #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
@@ -1842,7 +1846,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_PLAT_NUM_IO_APICS
   #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
 #else
-  #define CFG_PLAT_NUM_IO_APICS            0
+  #define CFG_PLAT_NUM_IO_APICS            3
 #endif
 
 #ifdef BLDCFG_MEM_INIT_PSTATE
@@ -1896,19 +1900,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
   #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
 #else
-  #define CFG_CSTATE_IO_BASE_ADDRESS       0
+  #define CFG_CSTATE_IO_BASE_ADDRESS       0x1770
 #endif
 
 #ifdef BLDCFG_PLATFORM_CPB_MODE
   #define CFG_CPB_MODE                        BLDCFG_PLATFORM_CPB_MODE
 #else
-  #define CFG_CPB_MODE                        CpbModeAuto
+  #define CFG_CPB_MODE                        CpbModeDisabled
 #endif
 
 #ifdef BLDCFG_CORE_LEVELING_MODE
   #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
 #else
-  #define CFG_CORE_LEVELING_MODE           0
+  #define CFG_CORE_LEVELING_MODE           CORE_LEVEL_LOWEST
 #endif
 
 #ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
@@ -1926,7 +1930,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
   #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
 #else
-  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR1866_FREQUENCY
 #endif
 
 #ifdef BLDCFG_MEMORY_MODE_UNGANGED
@@ -1998,13 +2002,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_POWER_DOWN
   #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
 #else
-  #define CFG_MEMORY_POWER_DOWN                 FALSE
+  #define CFG_MEMORY_POWER_DOWN                 TRUE
 #endif
 
 #ifdef BLDCFG_POWER_DOWN_MODE
   #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
 #else
-  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_MODE_AUTO
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHIP_SELECT
 #endif
 
 #ifdef BLDCFG_ONLINE_SPARE
@@ -2034,7 +2038,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_CLOCK_SELECT
   #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
 #else
-  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+  #define CFG_MEMORY_CLOCK_SELECT               DDR1866_FREQUENCY
 #endif
 
 #ifdef BLDCFG_DQS_TRAINING_CONTROL
@@ -2112,7 +2116,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_ECC_SYMBOL_SIZE
   #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
 #else
-  #define CFG_ECC_SYMBOL_SIZE         0
+  #define CFG_ECC_SYMBOL_SIZE         4
 #endif
 
 #ifdef BLDCFG_1GB_ALIGN
@@ -2148,7 +2152,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_UMA_ALIGNMENT
   #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
 #else
-  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+  #define CFG_UMA_ALIGNMENT           UMA_4MB_ALIGNED
 #endif
 
 #ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
@@ -2208,7 +2212,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
   #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
 #else
-  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+  #define CFG_LCD_BACK_LIGHT_CONTROL         200
 #endif
 
 #ifdef BLDCFG_STEREO_3D_PINOUT
@@ -2273,10 +2277,11 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
   #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               0
 #endif
 
+/* PCIe Spread Spectrum default value: 0.36% */
 #ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
   #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
 #else
-  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               0
+  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               36
 #endif
 
 #ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
@@ -2348,13 +2353,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
   #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
 #else
-  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         0
+  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         3
 #endif
 
 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
   #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
 #else
-  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         0
+  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         3
 #endif
 
 #ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
index 3e5137c655ac..a965a1d7d9c8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h
@@ -236,7 +236,7 @@ CpuLateInitApTask (
   #endif
   #define     SCOPE_NAME_VALUE    OEM_SCOPE_NAME
 #else
-  #define     SCOPE_NAME_VALUE    SCOPE_NAME_C
+  #define     SCOPE_NAME_VALUE    SCOPE_NAME_P
 #endif  // OEM_SCOPE_NAME
 
 #ifdef OEM_SCOPE_NAME1
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
index 47255041596a..64b71ef71364 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
@@ -48,6 +48,47 @@
   #define  FCH_SUPPORT   FALSE
 #endif
 
+/* Define the default values for the FCH configuration settings */
+#define DFLT_SMBUS0_BASE_ADDRESS		0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS		0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS		0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS		0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS		0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS		0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS		0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS		0x820
+#define DFLT_SPI_BASE_ADDRESS			0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS	0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS			0xFED00000
+#define DFLT_SMI_CMD_PORT			0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS		0xFE00
+#define DFLT_GEC_BASE_ADDRESS			0xFED61000
+#define DFLT_AZALIA_SSID			0x780D1022
+#define DFLT_SMBUS_SSID				0x780B1022
+#define DFLT_IDE_SSID				0x780C1022
+#define DFLT_SATA_AHCI_SSID			0x78011022
+#define DFLT_SATA_IDE_SSID			0x78001022
+#define DFLT_SATA_RAID5_SSID			0x78031022
+#define DFLT_SATA_RAID_SSID			0x78021022
+#define DFLT_EHCI_SSID				0x78081022
+#define DFLT_OHCI_SSID				0x78071022
+#define DFLT_LPC_SSID				0x780E1022
+#define DFLT_SD_SSID				0x78061022
+#define DFLT_XHCI_SSID				0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB		FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP		TRUE
+
+#define DFLT_FCH_GPP_LINK_CONFIG		PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT		FALSE
+
+#define DFLT_FCH_GPP_PORT0_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG		FALSE
 
 /* ACPI block register offset definitions */
 #define PM1_STATUS_OFFSET              0x00
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
index a648cc4ec3f3..7b1447199ad0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
@@ -160,7 +160,7 @@
   #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
     #define CFG_GNB_PCIE_TRAINING_ALGORITHM               BLDCFG_PCIE_TRAINING_ALGORITHM
   #else
-    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingStandard
+    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingDistributed
   #endif
 
   #ifndef CFG_GNB_FORCE_CABLESAFE_OFF
@@ -871,7 +871,7 @@
   #if (AGESA_ENTRY_INIT_S3SAVE == TRUE)
   //---------------------------------------------------------------------------------------------------
     #ifndef OPTION_GFX_INIT_SVIEW
-      #define OPTION_GFX_INIT_SVIEW TRUE
+      #define OPTION_GFX_INIT_SVIEW FALSE
     #endif
     #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
       OPTION_GNB_FEATURE                                  GfxInitSview;
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
index 686dfb153ab9..460644363231 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
@@ -310,7 +310,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
 
 #define OPTION_ACPI_PSTATES             TRUE
 #define OPTION_WHEA                     TRUE
-#define OPTION_DMI                      TRUE
+#define OPTION_DMI                      FALSE
 #define OPTION_EARLY_SAMPLES            FALSE
 #define CFG_ACPI_PSTATES_PPC            TRUE
 #define CFG_ACPI_PSTATES_PCT            TRUE
@@ -318,7 +318,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
 #define CFG_ACPI_PSTATES_PSS            TRUE
 #define CFG_ACPI_PSTATES_XPSS           TRUE
 #define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
 #define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
 #define OPTION_ALIB                     TRUE
 /*---------------------------------------------------------------------------
@@ -393,10 +393,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
     #define OPTION_PARALLEL_TRAINING    FALSE
   #endif
 #endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
-  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
     #undef  OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE         FALSE
+    #define OPTION_ONLINE_SPARE         TRUE
   #endif
 #endif
 #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
@@ -447,10 +448,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
     #define OPTION_WHEA                 FALSE
   #endif
 #endif
-#ifdef BLDOPT_REMOVE_DMI
-  #if  BLDOPT_REMOVE_DMI == TRUE
+/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
+#ifdef BLDOPT_ENABLE_DMI
+  #if  BLDOPT_ENABLE_DMI == TRUE
     #undef  OPTION_DMI
-    #define OPTION_DMI                  FALSE
+    #define OPTION_DMI                  TRUE
   #endif
 #endif
 #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
@@ -601,10 +603,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
     #define CFG_ACPI_PSTATES_PSD_POLICY     PsdPolicyProcessorDefault
 #endif
 
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
-  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
+#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
     #undef  CFG_VRM_HIGH_SPEED_ENABLE
-    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
   #endif
 #endif
 
@@ -752,7 +755,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_VRM_CURRENT_LIMIT
   #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
 #else
-  #define CFG_VRM_CURRENT_LIMIT            0
+  #define CFG_VRM_CURRENT_LIMIT            15000
 #endif
 
 #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
@@ -764,37 +767,37 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_VRM_SLEW_RATE
   #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
 #else
-  #define CFG_VRM_SLEW_RATE                (5000)
+  #define CFG_VRM_SLEW_RATE                (10000)
 #endif
 
 #ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
   #define CFG_VRM_MAXIMUM_CURRENT_LIMIT  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
 #else
-  #define CFG_VRM_MAXIMUM_CURRENT_LIMIT  (0)
+  #define CFG_VRM_MAXIMUM_CURRENT_LIMIT  (21000)
 #endif
 
 #ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
   #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT  BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
 #else
-  #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT  (0)
+  #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT  (17000)
 #endif
 
 #ifdef BLDCFG_VRM_SVI_OCP_LEVEL
   #define CFG_VRM_SVI_OCP_LEVEL     BLDCFG_VRM_SVI_OCP_LEVEL
 #else
-  #define CFG_VRM_SVI_OCP_LEVEL     0
+  #define CFG_VRM_SVI_OCP_LEVEL     CFG_VRM_MAXIMUM_CURRENT_LIMIT
 #endif
 
 #ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
   #define CFG_VRM_NB_SVI_OCP_LEVEL  BLDCFG_VRM_NB_SVI_OCP_LEVEL
 #else
-  #define CFG_VRM_NB_SVI_OCP_LEVEL  0
+  #define CFG_VRM_NB_SVI_OCP_LEVEL  CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
 #endif
 
 #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
   #define CFG_VRM_NB_CURRENT_LIMIT         BLDCFG_VRM_NB_CURRENT_LIMIT
 #else
-  #define CFG_VRM_NB_CURRENT_LIMIT         (0)
+  #define CFG_VRM_NB_CURRENT_LIMIT         (13000)
 #endif
 
 #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
@@ -806,13 +809,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_VRM_NB_SLEW_RATE
   #define CFG_VRM_NB_SLEW_RATE             BLDCFG_VRM_NB_SLEW_RATE
 #else
-  #define CFG_VRM_NB_SLEW_RATE             (5000)
+  #define CFG_VRM_NB_SLEW_RATE             CFG_VRM_SLEW_RATE
 #endif
 
 #ifdef BLDCFG_PLAT_NUM_IO_APICS
   #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
 #else
-  #define CFG_PLAT_NUM_IO_APICS            0
+  #define CFG_PLAT_NUM_IO_APICS            3
 #endif
 
 #ifdef BLDCFG_MEM_INIT_PSTATE
@@ -854,19 +857,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_PLATFORM_CSTATE_MODE
   #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
 #else
-  #define CFG_CSTATE_MODE                     CStateModeC6
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
 #endif
 
 #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
   #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
 #else
-  #define CFG_CSTATE_OPDATA                   0
+  #define CFG_CSTATE_OPDATA                   0x1770
 #endif
 
 #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
   #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
 #else
-  #define CFG_CSTATE_IO_BASE_ADDRESS       0
+  #define CFG_CSTATE_IO_BASE_ADDRESS       0x1770
 #endif
 
 #ifdef BLDCFG_PLATFORM_CPB_MODE
@@ -878,7 +881,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_CORE_LEVELING_MODE
   #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
 #else
-  #define CFG_CORE_LEVELING_MODE           0
+  #define CFG_CORE_LEVELING_MODE           CORE_LEVEL_LOWEST
 #endif
 
 #ifdef BLDCFG_AMD_TDP_LIMIT
@@ -896,7 +899,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
   #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
 #else
-  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR1866_FREQUENCY
 #endif
 
 #ifdef BLDCFG_MEMORY_MODE_UNGANGED
@@ -968,13 +971,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_POWER_DOWN
   #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
 #else
-  #define CFG_MEMORY_POWER_DOWN                 FALSE
+  #define CFG_MEMORY_POWER_DOWN                 TRUE
 #endif
 
 #ifdef BLDCFG_POWER_DOWN_MODE
   #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
 #else
-  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_MODE_AUTO
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHIP_SELECT
 #endif
 
 #ifdef BLDCFG_ONLINE_SPARE
@@ -1004,7 +1007,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_MEMORY_CLOCK_SELECT
   #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
 #else
-  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+  #define CFG_MEMORY_CLOCK_SELECT               DDR1866_FREQUENCY
 #endif
 
 #ifdef BLDCFG_DQS_TRAINING_CONTROL
@@ -1082,7 +1085,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_ECC_SYMBOL_SIZE
   #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
 #else
-  #define CFG_ECC_SYMBOL_SIZE         0
+  #define CFG_ECC_SYMBOL_SIZE         4
 #endif
 
 #ifdef BLDCFG_1GB_ALIGN
@@ -1118,7 +1121,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_UMA_ALIGNMENT
   #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
 #else
-  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+  #define CFG_UMA_ALIGNMENT           UMA_4MB_ALIGNED
 #endif
 
 #ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
@@ -1172,7 +1175,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_CFG_ABM_SUPPORT
   #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
 #else
-  #define CFG_ABM_SUPPORT                    FALSE
+  #define CFG_ABM_SUPPORT                    TRUE
 #endif
 
 #ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
@@ -1468,7 +1471,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #ifdef BLDCFG_GNB_IOAPIC_ADDRESS
   #define CFG_GNB_IOAPIC_ADDRESS             BLDCFG_GNB_IOAPIC_ADDRESS
 #else
-  #define CFG_GNB_IOAPIC_ADDRESS             NULL
+  #define CFG_GNB_IOAPIC_ADDRESS             0xFEC20000
 #endif
 
 #ifdef BLDCFG_GNB_IOMMU_ADDRESS
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h
index b27ed000572b..00ea0d7e9b9e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h
@@ -229,7 +229,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
   #endif
   #define     SCOPE_NAME_VALUE    OEM_SCOPE_NAME
 #else
-  #define     SCOPE_NAME_VALUE    SCOPE_NAME_C
+  #define     SCOPE_NAME_VALUE    SCOPE_NAME_P
 #endif  // OEM_SCOPE_NAME
 
 #ifdef OEM_SCOPE_NAME1