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| author | Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> | 2022-12-22 16:08:52 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-15 02:06:25 +0000 |
| commit | 4eba742ee6d25d507c9a5f253e53f13cdb7fcd16 (patch) | |
| tree | 33404ae7180366bd08c6df47b92a683b511451de /src | |
| parent | 429df8adbe91d0cf77369a3070b3d206d50a8890 (diff) | |
| download | coreboot-4eba742ee6d25d507c9a5f253e53f13cdb7fcd16.tar.gz coreboot-4eba742ee6d25d507c9a5f253e53f13cdb7fcd16.tar.bz2 coreboot-4eba742ee6d25d507c9a5f253e53f13cdb7fcd16.zip | |
mb/google/brya/var/marasov: Update Aux settings
Follow hardware design to correct aux setting on USB-C ports to
fix DP monitor can not output data through type-C port 0
USB-C port 0 did not have retimer.
USB-C port 1 have retimer.
USB-C port 0 AUX_DC_P connect to GPP_E22.
USB-C port 0 AUX_DC_N connect to GPP_E23.
BUG=b:263212450
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
DP monitor display normally
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/marasov/overridetree.cb | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 78da91fc3e69..db244b9964e9 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -88,6 +88,17 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) are allocated for TCSS Port1 configuration and Bits (2,3) for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0, Bit2 set to "1" indicates no retimer on USB-C Ports + # Bit1, Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USB-C connector + register "tcss_aux_ori" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, + .pad_auxn_dc = GPP_E23}" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_Port 1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C2 @@ -104,9 +115,7 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3 Port 2 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 - register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[1]" = "TCSS_PORT_EMPTY" - register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)" register "tcc_offset" = "5" # TCC of 100 |