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author | Shelley Chen <shchen@google.com> | 2022-11-29 13:48:58 -0800 |
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committer | Shelley Chen <shchen@google.com> | 2022-11-30 21:53:45 +0000 |
commit | cd4e3d52eeb02a705e0c28417d546c4de24e0ba5 (patch) | |
tree | 1e27d07c4387473a19560c2b2a23549e8fdc91f5 /src | |
parent | 474da028ab436c9668d2c9a5142c5f1ab9460044 (diff) | |
download | coreboot-cd4e3d52eeb02a705e0c28417d546c4de24e0ba5.tar.gz coreboot-cd4e3d52eeb02a705e0c28417d546c4de24e0ba5.tar.bz2 coreboot-cd4e3d52eeb02a705e0c28417d546c4de24e0ba5.zip |
mb/google/herobrine: Mask out upper bits from sku_id()
When retrieving the SKU id value through the sku_id() function in
mainboard_needs_pcie_init(), we only want the values in the lower 5
bits as we can only represent SKU id up to 27. Everything in the
higher bits should be masked out because they are not needed.
BUG=b:254281839
BRANCH=None
TEST=Make sure that NVMe is not initialized
Tested on a herobrine board with SKU id 0
Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70164
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/herobrine/mainboard.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index 2648392227ae..c9bca737e5d1 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -91,7 +91,12 @@ static void display_startup(void) */ bool mainboard_needs_pcie_init(void) { - uint32_t sku = sku_id(); + /* + * Mask out everything above the actual SKU bits We have 3 sku pins, + * each tristate, so we can represent numbers up to 27, or 5 bits + */ + uint32_t sku_bits_mask = 0xff; + uint32_t sku = sku_id() & sku_bits_mask; if (sku == CROS_SKU_UNKNOWN) { printk(BIOS_WARNING, "Unknown SKU (%#x); assuming PCIe", sku); |